\section{aversive\_\-10-03-12/include/aversive/parts/ATmega32M1.h File Reference}
\label{ATmega32M1_8h}\index{aversive\_\-10-03-12/include/aversive/parts/ATmega32M1.h@{aversive\_\-10-03-12/include/aversive/parts/ATmega32M1.h}}
\subsection*{Defines}
\begin{CompactItemize}
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-0}~0
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-1}~1
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-8}~2
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-64}~3
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-256}~4
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-1024}~5
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-FALL}~6
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-DIV\_\-RISE}~7
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-0}~0
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-1}~1
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-2}~8
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-3}~64
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-4}~256
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-5}~1024
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-6}~-1
\item 
\#define {\bf TIMER0\_\-PRESCALER\_\-REG\_\-7}~-2
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-0}~0
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-1}~1
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-8}~2
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-64}~3
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-256}~4
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-1024}~5
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-FALL}~6
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-DIV\_\-RISE}~7
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-0}~0
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-1}~1
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-2}~8
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-3}~64
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-4}~256
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-5}~1024
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-6}~-1
\item 
\#define {\bf TIMER1\_\-PRESCALER\_\-REG\_\-7}~-2
\item 
\#define {\bf TIMER0\_\-AVAILABLE}
\item 
\#define {\bf TIMER0A\_\-AVAILABLE}
\item 
\#define {\bf TIMER0B\_\-AVAILABLE}
\item 
\#define {\bf TIMER1\_\-AVAILABLE}
\item 
\#define {\bf TIMER1A\_\-AVAILABLE}
\item 
\#define {\bf TIMER1B\_\-AVAILABLE}
\item 
\#define {\bf SIG\_\-OVERFLOW0\_\-NUM}~0
\item 
\#define {\bf SIG\_\-OVERFLOW1\_\-NUM}~1
\item 
\#define {\bf SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM}~2
\item 
\#define {\bf SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM}~0
\item 
\#define {\bf SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM}~1
\item 
\#define {\bf SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM}~2
\item 
\#define {\bf SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM}~3
\item 
\#define {\bf SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM}~4
\item 
\#define {\bf PWM0A\_\-NUM}~0
\item 
\#define {\bf PWM0B\_\-NUM}~1
\item 
\#define {\bf PWM1A\_\-NUM}~2
\item 
\#define {\bf PWM1B\_\-NUM}~3
\item 
\#define {\bf PWM\_\-TOTAL\_\-NUM}~4
\item 
\#define {\bf SIG\_\-INPUT\_\-CAPTURE1\_\-NUM}~0
\item 
\#define {\bf SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM}~1
\item 
\#define {\bf PORTB0\_\-REG}~PORTB
\item 
\#define {\bf PORTB1\_\-REG}~PORTB
\item 
\#define {\bf PORTB2\_\-REG}~PORTB
\item 
\#define {\bf PORTB3\_\-REG}~PORTB
\item 
\#define {\bf PORTB4\_\-REG}~PORTB
\item 
\#define {\bf PORTB5\_\-REG}~PORTB
\item 
\#define {\bf PORTB6\_\-REG}~PORTB
\item 
\#define {\bf PORTB7\_\-REG}~PORTB
\item 
\#define {\bf LBT0\_\-REG}~LINBTR
\item 
\#define {\bf LBT1\_\-REG}~LINBTR
\item 
\#define {\bf LBT2\_\-REG}~LINBTR
\item 
\#define {\bf LBT3\_\-REG}~LINBTR
\item 
\#define {\bf LBT4\_\-REG}~LINBTR
\item 
\#define {\bf LBT5\_\-REG}~LINBTR
\item 
\#define {\bf LDISR\_\-REG}~LINBTR
\item 
\#define {\bf POCR1RA\_\-0\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-1\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-2\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-3\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-4\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-5\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-6\_\-REG}~POCR1RAL
\item 
\#define {\bf POCR1RA\_\-7\_\-REG}~POCR1RAL
\item 
\#define {\bf LID0\_\-REG}~LINIDR
\item 
\#define {\bf LID1\_\-REG}~LINIDR
\item 
\#define {\bf LID2\_\-REG}~LINIDR
\item 
\#define {\bf LID3\_\-REG}~LINIDR
\item 
\#define {\bf LID4\_\-REG}~LINIDR
\item 
\#define {\bf LID5\_\-REG}~LINIDR
\item 
\#define {\bf LP0\_\-REG}~LINIDR
\item 
\#define {\bf LP1\_\-REG}~LINIDR
\item 
\#define {\bf POCR1RA\_\-8\_\-REG}~POCR1RAH
\item 
\#define {\bf POCR1RA\_\-9\_\-REG}~POCR1RAH
\item 
\#define {\bf POCR1RA\_\-00\_\-REG}~POCR1RAH
\item 
\#define {\bf POCR1RA\_\-01\_\-REG}~POCR1RAH
\item 
\#define {\bf WDP0\_\-REG}~WDTCSR
\item 
\#define {\bf WDP1\_\-REG}~WDTCSR
\item 
\#define {\bf WDP2\_\-REG}~WDTCSR
\item 
\#define {\bf WDE\_\-REG}~WDTCSR
\item 
\#define {\bf WDCE\_\-REG}~WDTCSR
\item 
\#define {\bf WDP3\_\-REG}~WDTCSR
\item 
\#define {\bf WDIE\_\-REG}~WDTCSR
\item 
\#define {\bf WDIF\_\-REG}~WDTCSR
\item 
\#define {\bf EEDR0\_\-REG}~EEDR
\item 
\#define {\bf EEDR1\_\-REG}~EEDR
\item 
\#define {\bf EEDR2\_\-REG}~EEDR
\item 
\#define {\bf EEDR3\_\-REG}~EEDR
\item 
\#define {\bf EEDR4\_\-REG}~EEDR
\item 
\#define {\bf EEDR5\_\-REG}~EEDR
\item 
\#define {\bf EEDR6\_\-REG}~EEDR
\item 
\#define {\bf EEDR7\_\-REG}~EEDR
\item 
\#define {\bf LINDX0\_\-REG}~LINSEL
\item 
\#define {\bf LINDX1\_\-REG}~LINSEL
\item 
\#define {\bf LINDX2\_\-REG}~LINSEL
\item 
\#define {\bf LAINC\_\-REG}~LINSEL
\item 
\#define {\bf LCMD0\_\-REG}~LINCR
\item 
\#define {\bf LCMD1\_\-REG}~LINCR
\item 
\#define {\bf LCMD2\_\-REG}~LINCR
\item 
\#define {\bf LENA\_\-REG}~LINCR
\item 
\#define {\bf LCONF0\_\-REG}~LINCR
\item 
\#define {\bf LCONF1\_\-REG}~LINCR
\item 
\#define {\bf LIN13\_\-REG}~LINCR
\item 
\#define {\bf LSWRES\_\-REG}~LINCR
\item 
\#define {\bf PEOPE\_\-REG}~PIM
\item 
\#define {\bf PEVE0\_\-REG}~PIM
\item 
\#define {\bf PEVE1\_\-REG}~PIM
\item 
\#define {\bf PEVE2\_\-REG}~PIM
\item 
\#define {\bf POCR2SB\_\-0\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-1\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-2\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-3\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-4\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-5\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-6\_\-REG}~POCR2SBL
\item 
\#define {\bf POCR2SB\_\-7\_\-REG}~POCR2SBL
\item 
\#define {\bf SPI2X\_\-REG}~SPSR
\item 
\#define {\bf WCOL\_\-REG}~SPSR
\item 
\#define {\bf SPIF\_\-REG}~SPSR
\item 
\#define {\bf POCR2SB\_\-8\_\-REG}~POCR2SBH
\item 
\#define {\bf POCR2SB\_\-9\_\-REG}~POCR2SBH
\item 
\#define {\bf POCR2SB\_\-00\_\-REG}~POCR2SBH
\item 
\#define {\bf POCR2SB\_\-01\_\-REG}~POCR2SBH
\item 
\#define {\bf ICR1H0\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H1\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H2\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H3\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H4\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H5\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H6\_\-REG}~ICR1H
\item 
\#define {\bf ICR1H7\_\-REG}~ICR1H
\item 
\#define {\bf ICR1L0\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L1\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L2\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L3\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L4\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L5\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L6\_\-REG}~ICR1L
\item 
\#define {\bf ICR1L7\_\-REG}~ICR1L
\item 
\#define {\bf AC1M0\_\-REG}~AC1CON
\item 
\#define {\bf AC1M1\_\-REG}~AC1CON
\item 
\#define {\bf AC1M2\_\-REG}~AC1CON
\item 
\#define {\bf AC1ICE\_\-REG}~AC1CON
\item 
\#define {\bf AC1IS0\_\-REG}~AC1CON
\item 
\#define {\bf AC1IS1\_\-REG}~AC1CON
\item 
\#define {\bf AC1IE\_\-REG}~AC1CON
\item 
\#define {\bf AC1EN\_\-REG}~AC1CON
\item 
\#define {\bf PRADC\_\-REG}~PRR
\item 
\#define {\bf PRLIN\_\-REG}~PRR
\item 
\#define {\bf PRSPI\_\-REG}~PRR
\item 
\#define {\bf PRTIM0\_\-REG}~PRR
\item 
\#define {\bf PRTIM1\_\-REG}~PRR
\item 
\#define {\bf PRPSC\_\-REG}~PRR
\item 
\#define {\bf PRCAN\_\-REG}~PRR
\item 
\#define {\bf MUX0\_\-REG}~ADMUX
\item 
\#define {\bf MUX1\_\-REG}~ADMUX
\item 
\#define {\bf MUX2\_\-REG}~ADMUX
\item 
\#define {\bf MUX3\_\-REG}~ADMUX
\item 
\#define {\bf MUX4\_\-REG}~ADMUX
\item 
\#define {\bf ADLAR\_\-REG}~ADMUX
\item 
\#define {\bf REFS0\_\-REG}~ADMUX
\item 
\#define {\bf REFS1\_\-REG}~ADMUX
\item 
\#define {\bf LDIV0\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV1\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV2\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV3\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV4\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV5\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV6\_\-REG}~LINBRRL
\item 
\#define {\bf LDIV7\_\-REG}~LINBRRL
\item 
\#define {\bf EEAR8\_\-REG}~EEARH
\item 
\#define {\bf EEAR9\_\-REG}~EEARH
\item 
\#define {\bf LDIV8\_\-REG}~LINBRRH
\item 
\#define {\bf LDIV9\_\-REG}~LINBRRH
\item 
\#define {\bf LDIV10\_\-REG}~LINBRRH
\item 
\#define {\bf LDIV11\_\-REG}~LINBRRH
\item 
\#define {\bf ERRP\_\-REG}~CANGSTA
\item 
\#define {\bf BOFF\_\-REG}~CANGSTA
\item 
\#define {\bf ENFG\_\-REG}~CANGSTA
\item 
\#define {\bf RXBSY\_\-REG}~CANGSTA
\item 
\#define {\bf TXBSY\_\-REG}~CANGSTA
\item 
\#define {\bf OVFG\_\-REG}~CANGSTA
\item 
\#define {\bf SWRES\_\-REG}~CANGCON
\item 
\#define {\bf ENASTB\_\-REG}~CANGCON
\item 
\#define {\bf TEST\_\-REG}~CANGCON
\item 
\#define {\bf LISTEN\_\-REG}~CANGCON
\item 
\#define {\bf SYNTTC\_\-REG}~CANGCON
\item 
\#define {\bf TTC\_\-REG}~CANGCON
\item 
\#define {\bf OVRQ\_\-REG}~CANGCON
\item 
\#define {\bf ABRQ\_\-REG}~CANGCON
\item 
\#define {\bf PORTD0\_\-REG}~PORTD
\item 
\#define {\bf PORTD1\_\-REG}~PORTD
\item 
\#define {\bf PORTD2\_\-REG}~PORTD
\item 
\#define {\bf PORTD3\_\-REG}~PORTD
\item 
\#define {\bf PORTD4\_\-REG}~PORTD
\item 
\#define {\bf PORTD5\_\-REG}~PORTD
\item 
\#define {\bf PORTD6\_\-REG}~PORTD
\item 
\#define {\bf PORTD7\_\-REG}~PORTD
\item 
\#define {\bf PORTE0\_\-REG}~PORTE
\item 
\#define {\bf PORTE1\_\-REG}~PORTE
\item 
\#define {\bf PORTE2\_\-REG}~PORTE
\item 
\#define {\bf TCNT1H0\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H1\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H2\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H3\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H4\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H5\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H6\_\-REG}~TCNT1H
\item 
\#define {\bf TCNT1H7\_\-REG}~TCNT1H
\item 
\#define {\bf PORTC0\_\-REG}~PORTC
\item 
\#define {\bf PORTC1\_\-REG}~PORTC
\item 
\#define {\bf PORTC2\_\-REG}~PORTC
\item 
\#define {\bf PORTC3\_\-REG}~PORTC
\item 
\#define {\bf PORTC4\_\-REG}~PORTC
\item 
\#define {\bf PORTC5\_\-REG}~PORTC
\item 
\#define {\bf PORTC6\_\-REG}~PORTC
\item 
\#define {\bf PORTC7\_\-REG}~PORTC
\item 
\#define {\bf AMP1TS0\_\-REG}~AMP1CSR
\item 
\#define {\bf AMP1TS1\_\-REG}~AMP1CSR
\item 
\#define {\bf AMP1TS2\_\-REG}~AMP1CSR
\item 
\#define {\bf AMPCMP1\_\-REG}~AMP1CSR
\item 
\#define {\bf AMP1G0\_\-REG}~AMP1CSR
\item 
\#define {\bf AMP1G1\_\-REG}~AMP1CSR
\item 
\#define {\bf AMP1IS\_\-REG}~AMP1CSR
\item 
\#define {\bf AMP1EN\_\-REG}~AMP1CSR
\item 
\#define {\bf AC2M0\_\-REG}~AC2CON
\item 
\#define {\bf AC2M1\_\-REG}~AC2CON
\item 
\#define {\bf AC2M2\_\-REG}~AC2CON
\item 
\#define {\bf AC2IS0\_\-REG}~AC2CON
\item 
\#define {\bf AC2IS1\_\-REG}~AC2CON
\item 
\#define {\bf AC2IE\_\-REG}~AC2CON
\item 
\#define {\bf AC2EN\_\-REG}~AC2CON
\item 
\#define {\bf INDX0\_\-REG}~CANPAGE
\item 
\#define {\bf INDX1\_\-REG}~CANPAGE
\item 
\#define {\bf INDX2\_\-REG}~CANPAGE
\item 
\#define {\bf AINC\_\-REG}~CANPAGE
\item 
\#define {\bf MOBNB0\_\-REG}~CANPAGE
\item 
\#define {\bf MOBNB1\_\-REG}~CANPAGE
\item 
\#define {\bf MOBNB2\_\-REG}~CANPAGE
\item 
\#define {\bf MOBNB3\_\-REG}~CANPAGE
\item 
\#define {\bf INT0\_\-REG}~EIMSK
\item 
\#define {\bf INT1\_\-REG}~EIMSK
\item 
\#define {\bf INT2\_\-REG}~EIMSK
\item 
\#define {\bf INT3\_\-REG}~EIMSK
\item 
\#define {\bf LENRXOK\_\-REG}~LINENIR
\item 
\#define {\bf LENTXOK\_\-REG}~LINENIR
\item 
\#define {\bf LENIDOK\_\-REG}~LINENIR
\item 
\#define {\bf LENERR\_\-REG}~LINENIR
\item 
\#define {\bf ISC00\_\-REG}~EICRA
\item 
\#define {\bf ISC01\_\-REG}~EICRA
\item 
\#define {\bf ISC10\_\-REG}~EICRA
\item 
\#define {\bf ISC11\_\-REG}~EICRA
\item 
\#define {\bf ISC20\_\-REG}~EICRA
\item 
\#define {\bf ISC21\_\-REG}~EICRA
\item 
\#define {\bf ISC30\_\-REG}~EICRA
\item 
\#define {\bf ISC31\_\-REG}~EICRA
\item 
\#define {\bf POCR2RA\_\-0\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-1\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-2\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-3\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-4\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-5\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-6\_\-REG}~POCR2RAL
\item 
\#define {\bf POCR2RA\_\-7\_\-REG}~POCR2RAL
\item 
\#define {\bf ADC0D\_\-REG}~DIDR0
\item 
\#define {\bf ADC1D\_\-REG}~DIDR0
\item 
\#define {\bf ADC2D\_\-REG}~DIDR0
\item 
\#define {\bf ADC3D\_\-REG}~DIDR0
\item 
\#define {\bf ADC4D\_\-REG}~DIDR0
\item 
\#define {\bf ADC5D\_\-REG}~DIDR0
\item 
\#define {\bf ADC6D\_\-REG}~DIDR0
\item 
\#define {\bf ADC7D\_\-REG}~DIDR0
\item 
\#define {\bf ADC8D\_\-REG}~DIDR1
\item 
\#define {\bf ADC9D\_\-REG}~DIDR1
\item 
\#define {\bf ADC10D\_\-REG}~DIDR1
\item 
\#define {\bf AMP0ND\_\-REG}~DIDR1
\item 
\#define {\bf AMP0PD\_\-REG}~DIDR1
\item 
\#define {\bf ACMP0D\_\-REG}~DIDR1
\item 
\#define {\bf AMP2PD\_\-REG}~DIDR1
\item 
\#define {\bf POCR2RA\_\-8\_\-REG}~POCR2RAH
\item 
\#define {\bf POCR2RA\_\-9\_\-REG}~POCR2RAH
\item 
\#define {\bf POCR2RA\_\-00\_\-REG}~POCR2RAH
\item 
\#define {\bf POCR2RA\_\-01\_\-REG}~POCR2RAH
\item 
\#define {\bf CLKPS0\_\-REG}~CLKPR
\item 
\#define {\bf CLKPS1\_\-REG}~CLKPR
\item 
\#define {\bf CLKPS2\_\-REG}~CLKPR
\item 
\#define {\bf CLKPS3\_\-REG}~CLKPR
\item 
\#define {\bf CLKPCE\_\-REG}~CLKPR
\item 
\#define {\bf POCR1SA\_\-8\_\-REG}~POCR1SAH
\item 
\#define {\bf POCR1SA\_\-9\_\-REG}~POCR1SAH
\item 
\#define {\bf POCR1SA\_\-00\_\-REG}~POCR1SAH
\item 
\#define {\bf POCR1SA\_\-01\_\-REG}~POCR1SAH
\item 
\#define {\bf POCR1SA\_\-0\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-1\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-2\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-3\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-4\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-5\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-6\_\-REG}~POCR1SAL
\item 
\#define {\bf POCR1SA\_\-7\_\-REG}~POCR1SAL
\item 
\#define {\bf IDMSK21\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK22\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK23\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK24\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK25\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK26\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK27\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK28\_\-REG}~CANIDM1
\item 
\#define {\bf IDMSK5\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK6\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK7\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK8\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK9\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK10\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK11\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK12\_\-REG}~CANIDM3
\item 
\#define {\bf IDMSK13\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK14\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK15\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK16\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK17\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK18\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK19\_\-REG}~CANIDM2
\item 
\#define {\bf IDMSK20\_\-REG}~CANIDM2
\item 
\#define {\bf IDEMSK\_\-REG}~CANIDM4
\item 
\#define {\bf RTRMSK\_\-REG}~CANIDM4
\item 
\#define {\bf IDMSK0\_\-REG}~CANIDM4
\item 
\#define {\bf IDMSK1\_\-REG}~CANIDM4
\item 
\#define {\bf IDMSK2\_\-REG}~CANIDM4
\item 
\#define {\bf IDMSK3\_\-REG}~CANIDM4
\item 
\#define {\bf IDMSK4\_\-REG}~CANIDM4
\item 
\#define {\bf DDB0\_\-REG}~DDRB
\item 
\#define {\bf DDB1\_\-REG}~DDRB
\item 
\#define {\bf DDB2\_\-REG}~DDRB
\item 
\#define {\bf DDB3\_\-REG}~DDRB
\item 
\#define {\bf DDB4\_\-REG}~DDRB
\item 
\#define {\bf DDB5\_\-REG}~DDRB
\item 
\#define {\bf DDB6\_\-REG}~DDRB
\item 
\#define {\bf DDB7\_\-REG}~DDRB
\item 
\#define {\bf DDC0\_\-REG}~DDRC
\item 
\#define {\bf DDC1\_\-REG}~DDRC
\item 
\#define {\bf DDC2\_\-REG}~DDRC
\item 
\#define {\bf DDC3\_\-REG}~DDRC
\item 
\#define {\bf DDC4\_\-REG}~DDRC
\item 
\#define {\bf DDC5\_\-REG}~DDRC
\item 
\#define {\bf DDC6\_\-REG}~DDRC
\item 
\#define {\bf DDC7\_\-REG}~DDRC
\item 
\#define {\bf PRFM20\_\-REG}~PMIC2
\item 
\#define {\bf PRFM21\_\-REG}~PMIC2
\item 
\#define {\bf PRFM22\_\-REG}~PMIC2
\item 
\#define {\bf PAOC2\_\-REG}~PMIC2
\item 
\#define {\bf PFLTE2\_\-REG}~PMIC2
\item 
\#define {\bf PELEV2\_\-REG}~PMIC2
\item 
\#define {\bf PISEL2\_\-REG}~PMIC2
\item 
\#define {\bf POVEN2\_\-REG}~PMIC2
\item 
\#define {\bf FOC1B\_\-REG}~TCCR1C
\item 
\#define {\bf FOC1A\_\-REG}~TCCR1C
\item 
\#define {\bf PRFM10\_\-REG}~PMIC1
\item 
\#define {\bf PRFM11\_\-REG}~PMIC1
\item 
\#define {\bf PRFM12\_\-REG}~PMIC1
\item 
\#define {\bf PAOC1\_\-REG}~PMIC1
\item 
\#define {\bf PFLTE1\_\-REG}~PMIC1
\item 
\#define {\bf PELEV1\_\-REG}~PMIC1
\item 
\#define {\bf PISEL1\_\-REG}~PMIC1
\item 
\#define {\bf POVEN1\_\-REG}~PMIC1
\item 
\#define {\bf CAL0\_\-REG}~OSCCAL
\item 
\#define {\bf CAL1\_\-REG}~OSCCAL
\item 
\#define {\bf CAL2\_\-REG}~OSCCAL
\item 
\#define {\bf CAL3\_\-REG}~OSCCAL
\item 
\#define {\bf CAL4\_\-REG}~OSCCAL
\item 
\#define {\bf CAL5\_\-REG}~OSCCAL
\item 
\#define {\bf CAL6\_\-REG}~OSCCAL
\item 
\#define {\bf DDD0\_\-REG}~DDRD
\item 
\#define {\bf DDD1\_\-REG}~DDRD
\item 
\#define {\bf DDD2\_\-REG}~DDRD
\item 
\#define {\bf DDD3\_\-REG}~DDRD
\item 
\#define {\bf DDD4\_\-REG}~DDRD
\item 
\#define {\bf DDD5\_\-REG}~DDRD
\item 
\#define {\bf DDD6\_\-REG}~DDRD
\item 
\#define {\bf DDD7\_\-REG}~DDRD
\item 
\#define {\bf PRUN\_\-REG}~PCTL
\item 
\#define {\bf PCCYC\_\-REG}~PCTL
\item 
\#define {\bf PCLKSEL\_\-REG}~PCTL
\item 
\#define {\bf PPRE0\_\-REG}~PCTL
\item 
\#define {\bf PPRE1\_\-REG}~PCTL
\item 
\#define {\bf GPIOR10\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR11\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR12\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR13\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR14\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR15\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR16\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR17\_\-REG}~GPIOR1
\item 
\#define {\bf GPIOR00\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR01\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR02\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR03\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR04\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR05\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR06\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR07\_\-REG}~GPIOR0
\item 
\#define {\bf GPIOR20\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR21\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR22\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR23\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR24\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR25\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR26\_\-REG}~GPIOR2
\item 
\#define {\bf GPIOR27\_\-REG}~GPIOR2
\item 
\#define {\bf AERG\_\-REG}~CANGIT
\item 
\#define {\bf FERG\_\-REG}~CANGIT
\item 
\#define {\bf CERG\_\-REG}~CANGIT
\item 
\#define {\bf SERG\_\-REG}~CANGIT
\item 
\#define {\bf BXOK\_\-REG}~CANGIT
\item 
\#define {\bf OVRTIM\_\-REG}~CANGIT
\item 
\#define {\bf BOFFIT\_\-REG}~CANGIT
\item 
\#define {\bf CANIT\_\-REG}~CANGIT
\item 
\#define {\bf AC3M0\_\-REG}~AC3CON
\item 
\#define {\bf AC3M1\_\-REG}~AC3CON
\item 
\#define {\bf AC3M2\_\-REG}~AC3CON
\item 
\#define {\bf AC3IS0\_\-REG}~AC3CON
\item 
\#define {\bf AC3IS1\_\-REG}~AC3CON
\item 
\#define {\bf AC3IE\_\-REG}~AC3CON
\item 
\#define {\bf AC3EN\_\-REG}~AC3CON
\item 
\#define {\bf LBERR\_\-REG}~LINERR
\item 
\#define {\bf LCERR\_\-REG}~LINERR
\item 
\#define {\bf LPERR\_\-REG}~LINERR
\item 
\#define {\bf LSERR\_\-REG}~LINERR
\item 
\#define {\bf LFERR\_\-REG}~LINERR
\item 
\#define {\bf LOVERR\_\-REG}~LINERR
\item 
\#define {\bf LTOERR\_\-REG}~LINERR
\item 
\#define {\bf LABORT\_\-REG}~LINERR
\item 
\#define {\bf PCIE0\_\-REG}~PCICR
\item 
\#define {\bf PCIE1\_\-REG}~PCICR
\item 
\#define {\bf PCIE2\_\-REG}~PCICR
\item 
\#define {\bf PCIE3\_\-REG}~PCICR
\item 
\#define {\bf ENOVRT\_\-REG}~CANGIE
\item 
\#define {\bf ENERG\_\-REG}~CANGIE
\item 
\#define {\bf ENBX\_\-REG}~CANGIE
\item 
\#define {\bf ENERR\_\-REG}~CANGIE
\item 
\#define {\bf ENTX\_\-REG}~CANGIE
\item 
\#define {\bf ENRX\_\-REG}~CANGIE
\item 
\#define {\bf ENBOFF\_\-REG}~CANGIE
\item 
\#define {\bf ENIT\_\-REG}~CANGIE
\item 
\#define {\bf TCNT0\_\-0\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-1\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-2\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-3\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-4\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-5\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-6\_\-REG}~TCNT0
\item 
\#define {\bf TCNT0\_\-7\_\-REG}~TCNT0
\item 
\#define {\bf IEMOB0\_\-REG}~CANIE2
\item 
\#define {\bf IEMOB1\_\-REG}~CANIE2
\item 
\#define {\bf IEMOB2\_\-REG}~CANIE2
\item 
\#define {\bf IEMOB3\_\-REG}~CANIE2
\item 
\#define {\bf IEMOB4\_\-REG}~CANIE2
\item 
\#define {\bf IEMOB5\_\-REG}~CANIE2
\item 
\#define {\bf POCR0RA\_\-0\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-1\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-2\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-3\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-4\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-5\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-6\_\-REG}~POCR0RAL
\item 
\#define {\bf POCR0RA\_\-7\_\-REG}~POCR0RAL
\item 
\#define {\bf SIT0\_\-REG}~CANSIT2
\item 
\#define {\bf SIT1\_\-REG}~CANSIT2
\item 
\#define {\bf SIT2\_\-REG}~CANSIT2
\item 
\#define {\bf SIT3\_\-REG}~CANSIT2
\item 
\#define {\bf SIT4\_\-REG}~CANSIT2
\item 
\#define {\bf SIT5\_\-REG}~CANSIT2
\item 
\#define {\bf CS00\_\-REG}~TCCR0B
\item 
\#define {\bf CS01\_\-REG}~TCCR0B
\item 
\#define {\bf CS02\_\-REG}~TCCR0B
\item 
\#define {\bf WGM02\_\-REG}~TCCR0B
\item 
\#define {\bf FOC0B\_\-REG}~TCCR0B
\item 
\#define {\bf FOC0A\_\-REG}~TCCR0B
\item 
\#define {\bf POCR0RA\_\-8\_\-REG}~POCR0RAH
\item 
\#define {\bf POCR0RA\_\-9\_\-REG}~POCR0RAH
\item 
\#define {\bf POCR0RA\_\-00\_\-REG}~POCR0RAH
\item 
\#define {\bf POCR0RA\_\-01\_\-REG}~POCR0RAH
\item 
\#define {\bf WGM00\_\-REG}~TCCR0A
\item 
\#define {\bf WGM01\_\-REG}~TCCR0A
\item 
\#define {\bf COM0B0\_\-REG}~TCCR0A
\item 
\#define {\bf COM0B1\_\-REG}~TCCR0A
\item 
\#define {\bf COM0A0\_\-REG}~TCCR0A
\item 
\#define {\bf COM0A1\_\-REG}~TCCR0A
\item 
\#define {\bf POCR2SA\_\-8\_\-REG}~POCR2SAH
\item 
\#define {\bf POCR2SA\_\-9\_\-REG}~POCR2SAH
\item 
\#define {\bf POCR2SA\_\-00\_\-REG}~POCR2SAH
\item 
\#define {\bf POCR2SA\_\-01\_\-REG}~POCR2SAH
\item 
\#define {\bf POCR2SA\_\-0\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-1\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-2\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-3\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-4\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-5\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-6\_\-REG}~POCR2SAL
\item 
\#define {\bf POCR2SA\_\-7\_\-REG}~POCR2SAL
\item 
\#define {\bf DDE0\_\-REG}~DDRE
\item 
\#define {\bf DDE1\_\-REG}~DDRE
\item 
\#define {\bf DDE2\_\-REG}~DDRE
\item 
\#define {\bf SPR0\_\-REG}~SPCR
\item 
\#define {\bf SPR1\_\-REG}~SPCR
\item 
\#define {\bf CPHA\_\-REG}~SPCR
\item 
\#define {\bf CPOL\_\-REG}~SPCR
\item 
\#define {\bf MSTR\_\-REG}~SPCR
\item 
\#define {\bf DORD\_\-REG}~SPCR
\item 
\#define {\bf SPE\_\-REG}~SPCR
\item 
\#define {\bf SPIE\_\-REG}~SPCR
\item 
\#define {\bf TOV1\_\-REG}~TIFR1
\item 
\#define {\bf OCF1A\_\-REG}~TIFR1
\item 
\#define {\bf OCF1B\_\-REG}~TIFR1
\item 
\#define {\bf ICF1\_\-REG}~TIFR1
\item 
\#define {\bf RB0TAG\_\-REG}~CANIDT4
\item 
\#define {\bf RB1TAG\_\-REG}~CANIDT4
\item 
\#define {\bf RTRTAG\_\-REG}~CANIDT4
\item 
\#define {\bf IDT0\_\-REG}~CANIDT4
\item 
\#define {\bf IDT1\_\-REG}~CANIDT4
\item 
\#define {\bf IDT2\_\-REG}~CANIDT4
\item 
\#define {\bf IDT3\_\-REG}~CANIDT4
\item 
\#define {\bf IDT4\_\-REG}~CANIDT4
\item 
\#define {\bf SPDR0\_\-REG}~SPDR
\item 
\#define {\bf SPDR1\_\-REG}~SPDR
\item 
\#define {\bf SPDR2\_\-REG}~SPDR
\item 
\#define {\bf SPDR3\_\-REG}~SPDR
\item 
\#define {\bf SPDR4\_\-REG}~SPDR
\item 
\#define {\bf SPDR5\_\-REG}~SPDR
\item 
\#define {\bf SPDR6\_\-REG}~SPDR
\item 
\#define {\bf SPDR7\_\-REG}~SPDR
\item 
\#define {\bf IDT13\_\-REG}~CANIDT2
\item 
\#define {\bf IDT14\_\-REG}~CANIDT2
\item 
\#define {\bf IDT15\_\-REG}~CANIDT2
\item 
\#define {\bf IDT16\_\-REG}~CANIDT2
\item 
\#define {\bf IDT17\_\-REG}~CANIDT2
\item 
\#define {\bf IDT18\_\-REG}~CANIDT2
\item 
\#define {\bf IDT19\_\-REG}~CANIDT2
\item 
\#define {\bf IDT20\_\-REG}~CANIDT2
\item 
\#define {\bf IDT5\_\-REG}~CANIDT3
\item 
\#define {\bf IDT6\_\-REG}~CANIDT3
\item 
\#define {\bf IDT7\_\-REG}~CANIDT3
\item 
\#define {\bf IDT8\_\-REG}~CANIDT3
\item 
\#define {\bf IDT9\_\-REG}~CANIDT3
\item 
\#define {\bf IDT10\_\-REG}~CANIDT3
\item 
\#define {\bf IDT11\_\-REG}~CANIDT3
\item 
\#define {\bf IDT12\_\-REG}~CANIDT3
\item 
\#define {\bf IDT21\_\-REG}~CANIDT1
\item 
\#define {\bf IDT22\_\-REG}~CANIDT1
\item 
\#define {\bf IDT23\_\-REG}~CANIDT1
\item 
\#define {\bf IDT24\_\-REG}~CANIDT1
\item 
\#define {\bf IDT25\_\-REG}~CANIDT1
\item 
\#define {\bf IDT26\_\-REG}~CANIDT1
\item 
\#define {\bf IDT27\_\-REG}~CANIDT1
\item 
\#define {\bf IDT28\_\-REG}~CANIDT1
\item 
\#define {\bf PSYNC00\_\-REG}~PSYNC
\item 
\#define {\bf PSYNC01\_\-REG}~PSYNC
\item 
\#define {\bf PSYNC10\_\-REG}~PSYNC
\item 
\#define {\bf PSYNC11\_\-REG}~PSYNC
\item 
\#define {\bf PSYNC20\_\-REG}~PSYNC
\item 
\#define {\bf PSYNC21\_\-REG}~PSYNC
\item 
\#define {\bf PSR10\_\-REG}~GTCCR
\item 
\#define {\bf ICPSEL1\_\-REG}~GTCCR
\item 
\#define {\bf TSM\_\-REG}~GTCCR
\item 
\#define {\bf PSRSYNC\_\-REG}~GTCCR
\item 
\#define {\bf DLC0\_\-REG}~CANCDMOB
\item 
\#define {\bf DLC1\_\-REG}~CANCDMOB
\item 
\#define {\bf DLC2\_\-REG}~CANCDMOB
\item 
\#define {\bf DLC3\_\-REG}~CANCDMOB
\item 
\#define {\bf IDE\_\-REG}~CANCDMOB
\item 
\#define {\bf RPLV\_\-REG}~CANCDMOB
\item 
\#define {\bf CONMOB0\_\-REG}~CANCDMOB
\item 
\#define {\bf CONMOB1\_\-REG}~CANCDMOB
\item 
\#define {\bf SP8\_\-REG}~SPH
\item 
\#define {\bf SP9\_\-REG}~SPH
\item 
\#define {\bf SP10\_\-REG}~SPH
\item 
\#define {\bf SP11\_\-REG}~SPH
\item 
\#define {\bf SP12\_\-REG}~SPH
\item 
\#define {\bf SP13\_\-REG}~SPH
\item 
\#define {\bf SP14\_\-REG}~SPH
\item 
\#define {\bf SP15\_\-REG}~SPH
\item 
\#define {\bf CGP0\_\-REG}~CANHPMOB
\item 
\#define {\bf CGP1\_\-REG}~CANHPMOB
\item 
\#define {\bf CGP2\_\-REG}~CANHPMOB
\item 
\#define {\bf CGP3\_\-REG}~CANHPMOB
\item 
\#define {\bf HPMOB0\_\-REG}~CANHPMOB
\item 
\#define {\bf HPMOB1\_\-REG}~CANHPMOB
\item 
\#define {\bf HPMOB2\_\-REG}~CANHPMOB
\item 
\#define {\bf HPMOB3\_\-REG}~CANHPMOB
\item 
\#define {\bf OCR1BL0\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL1\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL2\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL3\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL4\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL5\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL6\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BL7\_\-REG}~OCR1BL
\item 
\#define {\bf OCR1BH0\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH1\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH2\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH3\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH4\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH5\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH6\_\-REG}~OCR1BH
\item 
\#define {\bf OCR1BH7\_\-REG}~OCR1BH
\item 
\#define {\bf SP0\_\-REG}~SPL
\item 
\#define {\bf SP1\_\-REG}~SPL
\item 
\#define {\bf SP2\_\-REG}~SPL
\item 
\#define {\bf SP3\_\-REG}~SPL
\item 
\#define {\bf SP4\_\-REG}~SPL
\item 
\#define {\bf SP5\_\-REG}~SPL
\item 
\#define {\bf SP6\_\-REG}~SPL
\item 
\#define {\bf SP7\_\-REG}~SPL
\item 
\#define {\bf PORF\_\-REG}~MCUSR
\item 
\#define {\bf EXTRF\_\-REG}~MCUSR
\item 
\#define {\bf BORF\_\-REG}~MCUSR
\item 
\#define {\bf WDRF\_\-REG}~MCUSR
\item 
\#define {\bf EERE\_\-REG}~EECR
\item 
\#define {\bf EEWE\_\-REG}~EECR
\item 
\#define {\bf EEMWE\_\-REG}~EECR
\item 
\#define {\bf EERIE\_\-REG}~EECR
\item 
\#define {\bf EEPM0\_\-REG}~EECR
\item 
\#define {\bf EEPM1\_\-REG}~EECR
\item 
\#define {\bf POCR1SB\_\-0\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-1\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-2\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-3\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-4\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-5\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-6\_\-REG}~POCR1SBL
\item 
\#define {\bf POCR1SB\_\-7\_\-REG}~POCR1SBL
\item 
\#define {\bf SE\_\-REG}~SMCR
\item 
\#define {\bf SM0\_\-REG}~SMCR
\item 
\#define {\bf SM1\_\-REG}~SMCR
\item 
\#define {\bf SM2\_\-REG}~SMCR
\item 
\#define {\bf PLOCK\_\-REG}~PLLCSR
\item 
\#define {\bf PLLE\_\-REG}~PLLCSR
\item 
\#define {\bf PLLF\_\-REG}~PLLCSR
\item 
\#define {\bf POCR1SB\_\-8\_\-REG}~POCR1SBH
\item 
\#define {\bf POCR1SB\_\-9\_\-REG}~POCR1SBH
\item 
\#define {\bf POCR1SB\_\-00\_\-REG}~POCR1SBH
\item 
\#define {\bf POCR1SB\_\-01\_\-REG}~POCR1SBH
\item 
\#define {\bf PCIF0\_\-REG}~PCIFR
\item 
\#define {\bf PCIF1\_\-REG}~PCIFR
\item 
\#define {\bf PCIF2\_\-REG}~PCIFR
\item 
\#define {\bf PCIF3\_\-REG}~PCIFR
\item 
\#define {\bf AMP2TS0\_\-REG}~AMP2CSR
\item 
\#define {\bf AMP2TS1\_\-REG}~AMP2CSR
\item 
\#define {\bf AMP2TS2\_\-REG}~AMP2CSR
\item 
\#define {\bf AMPCMP2\_\-REG}~AMP2CSR
\item 
\#define {\bf AMP2G0\_\-REG}~AMP2CSR
\item 
\#define {\bf AMP2G1\_\-REG}~AMP2CSR
\item 
\#define {\bf AMP2IS\_\-REG}~AMP2CSR
\item 
\#define {\bf AMP2EN\_\-REG}~AMP2CSR
\item 
\#define {\bf C\_\-REG}~SREG
\item 
\#define {\bf Z\_\-REG}~SREG
\item 
\#define {\bf N\_\-REG}~SREG
\item 
\#define {\bf V\_\-REG}~SREG
\item 
\#define {\bf S\_\-REG}~SREG
\item 
\#define {\bf H\_\-REG}~SREG
\item 
\#define {\bf T\_\-REG}~SREG
\item 
\#define {\bf I\_\-REG}~SREG
\item 
\#define {\bf LDATA0\_\-REG}~LINDAT
\item 
\#define {\bf LDATA1\_\-REG}~LINDAT
\item 
\#define {\bf LDATA2\_\-REG}~LINDAT
\item 
\#define {\bf LDATA3\_\-REG}~LINDAT
\item 
\#define {\bf LDATA4\_\-REG}~LINDAT
\item 
\#define {\bf LDATA5\_\-REG}~LINDAT
\item 
\#define {\bf LDATA6\_\-REG}~LINDAT
\item 
\#define {\bf LDATA7\_\-REG}~LINDAT
\item 
\#define {\bf POCR0SA\_\-8\_\-REG}~POCR0SAH
\item 
\#define {\bf POCR0SA\_\-9\_\-REG}~POCR0SAH
\item 
\#define {\bf POCR0SA\_\-00\_\-REG}~POCR0SAH
\item 
\#define {\bf POCR0SA\_\-01\_\-REG}~POCR0SAH
\item 
\#define {\bf POCR\_\-RB\_\-0\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-1\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-2\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-3\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-4\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-5\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-6\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR\_\-RB\_\-7\_\-REG}~POCR\_\-RBL
\item 
\#define {\bf POCR0SA\_\-0\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-1\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-2\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-3\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-4\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-5\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-6\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR0SA\_\-7\_\-REG}~POCR0SAL
\item 
\#define {\bf POCR\_\-RB\_\-8\_\-REG}~POCR\_\-RBH
\item 
\#define {\bf POCR\_\-RB\_\-9\_\-REG}~POCR\_\-RBH
\item 
\#define {\bf POCR\_\-RB\_\-00\_\-REG}~POCR\_\-RBH
\item 
\#define {\bf POCR\_\-RB\_\-01\_\-REG}~POCR\_\-RBH
\item 
\#define {\bf LRXDL0\_\-REG}~LINDLR
\item 
\#define {\bf LRXDL1\_\-REG}~LINDLR
\item 
\#define {\bf LRXDL2\_\-REG}~LINDLR
\item 
\#define {\bf LRXDL3\_\-REG}~LINDLR
\item 
\#define {\bf LTXDL0\_\-REG}~LINDLR
\item 
\#define {\bf LTXDL1\_\-REG}~LINDLR
\item 
\#define {\bf LTXDL2\_\-REG}~LINDLR
\item 
\#define {\bf LTXDL3\_\-REG}~LINDLR
\item 
\#define {\bf IVCE\_\-REG}~MCUCR
\item 
\#define {\bf IVSEL\_\-REG}~MCUCR
\item 
\#define {\bf PUD\_\-REG}~MCUCR
\item 
\#define {\bf SPIPS\_\-REG}~MCUCR
\item 
\#define {\bf EEAR0\_\-REG}~EEARL
\item 
\#define {\bf EEAR1\_\-REG}~EEARL
\item 
\#define {\bf EEAR2\_\-REG}~EEARL
\item 
\#define {\bf EEAR3\_\-REG}~EEARL
\item 
\#define {\bf EEAR4\_\-REG}~EEARL
\item 
\#define {\bf EEAR5\_\-REG}~EEARL
\item 
\#define {\bf EEAR6\_\-REG}~EEARL
\item 
\#define {\bf EEAR7\_\-REG}~EEARL
\item 
\#define {\bf INTF0\_\-REG}~EIFR
\item 
\#define {\bf INTF1\_\-REG}~EIFR
\item 
\#define {\bf INTF2\_\-REG}~EIFR
\item 
\#define {\bf INTF3\_\-REG}~EIFR
\item 
\#define {\bf AERR\_\-REG}~CANSTMOB
\item 
\#define {\bf FERR\_\-REG}~CANSTMOB
\item 
\#define {\bf CERR\_\-REG}~CANSTMOB
\item 
\#define {\bf SERR\_\-REG}~CANSTMOB
\item 
\#define {\bf BERR\_\-REG}~CANSTMOB
\item 
\#define {\bf RXOK\_\-REG}~CANSTMOB
\item 
\#define {\bf TXOK\_\-REG}~CANSTMOB
\item 
\#define {\bf DLCW\_\-REG}~CANSTMOB
\item 
\#define {\bf PEOP\_\-REG}~PIFR
\item 
\#define {\bf PEV0\_\-REG}~PIFR
\item 
\#define {\bf PEV1\_\-REG}~PIFR
\item 
\#define {\bf PEV2\_\-REG}~PIFR
\item 
\#define {\bf LRXOK\_\-REG}~LINSIR
\item 
\#define {\bf LTXOK\_\-REG}~LINSIR
\item 
\#define {\bf LIDOK\_\-REG}~LINSIR
\item 
\#define {\bf LERR\_\-REG}~LINSIR
\item 
\#define {\bf LBUSY\_\-REG}~LINSIR
\item 
\#define {\bf LIDST0\_\-REG}~LINSIR
\item 
\#define {\bf LIDST1\_\-REG}~LINSIR
\item 
\#define {\bf LIDST2\_\-REG}~LINSIR
\item 
\#define {\bf DACH0\_\-REG}~DACH
\item 
\#define {\bf DACH1\_\-REG}~DACH
\item 
\#define {\bf DACH2\_\-REG}~DACH
\item 
\#define {\bf DACH3\_\-REG}~DACH
\item 
\#define {\bf DACH4\_\-REG}~DACH
\item 
\#define {\bf DACH5\_\-REG}~DACH
\item 
\#define {\bf DACH6\_\-REG}~DACH
\item 
\#define {\bf DACH7\_\-REG}~DACH
\item 
\#define {\bf DACL0\_\-REG}~DACL
\item 
\#define {\bf DACL1\_\-REG}~DACL
\item 
\#define {\bf DACL2\_\-REG}~DACL
\item 
\#define {\bf DACL3\_\-REG}~DACL
\item 
\#define {\bf DACL4\_\-REG}~DACL
\item 
\#define {\bf DACL5\_\-REG}~DACL
\item 
\#define {\bf DACL6\_\-REG}~DACL
\item 
\#define {\bf DACL7\_\-REG}~DACL
\item 
\#define {\bf ENMOB0\_\-REG}~CANEN2
\item 
\#define {\bf ENMOB1\_\-REG}~CANEN2
\item 
\#define {\bf ENMOB2\_\-REG}~CANEN2
\item 
\#define {\bf ENMOB3\_\-REG}~CANEN2
\item 
\#define {\bf ENMOB4\_\-REG}~CANEN2
\item 
\#define {\bf ENMOB5\_\-REG}~CANEN2
\item 
\#define {\bf ADTS0\_\-REG}~ADCSRB
\item 
\#define {\bf ADTS1\_\-REG}~ADCSRB
\item 
\#define {\bf ADTS2\_\-REG}~ADCSRB
\item 
\#define {\bf ADTS3\_\-REG}~ADCSRB
\item 
\#define {\bf AREFEN\_\-REG}~ADCSRB
\item 
\#define {\bf ISRCEN\_\-REG}~ADCSRB
\item 
\#define {\bf ADHSM\_\-REG}~ADCSRB
\item 
\#define {\bf WGM10\_\-REG}~TCCR1A
\item 
\#define {\bf WGM11\_\-REG}~TCCR1A
\item 
\#define {\bf COM1B0\_\-REG}~TCCR1A
\item 
\#define {\bf COM1B1\_\-REG}~TCCR1A
\item 
\#define {\bf COM1A0\_\-REG}~TCCR1A
\item 
\#define {\bf COM1A1\_\-REG}~TCCR1A
\item 
\#define {\bf POCR0SB\_\-0\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-1\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-2\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-3\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-4\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-5\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-6\_\-REG}~POCR0SBL
\item 
\#define {\bf POCR0SB\_\-7\_\-REG}~POCR0SBL
\item 
\#define {\bf AC0O\_\-REG}~ACSR
\item 
\#define {\bf AC1O\_\-REG}~ACSR
\item 
\#define {\bf AC2O\_\-REG}~ACSR
\item 
\#define {\bf AC3O\_\-REG}~ACSR
\item 
\#define {\bf AC0IF\_\-REG}~ACSR
\item 
\#define {\bf AC1IF\_\-REG}~ACSR
\item 
\#define {\bf AC2IF\_\-REG}~ACSR
\item 
\#define {\bf AC3IF\_\-REG}~ACSR
\item 
\#define {\bf TCNT1L0\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L1\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L2\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L3\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L4\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L5\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L6\_\-REG}~TCNT1L
\item 
\#define {\bf TCNT1L7\_\-REG}~TCNT1L
\item 
\#define {\bf PRFM00\_\-REG}~PMIC0
\item 
\#define {\bf PRFM01\_\-REG}~PMIC0
\item 
\#define {\bf PRFM02\_\-REG}~PMIC0
\item 
\#define {\bf PAOC0\_\-REG}~PMIC0
\item 
\#define {\bf PFLTE0\_\-REG}~PMIC0
\item 
\#define {\bf PELEV0\_\-REG}~PMIC0
\item 
\#define {\bf PISEL0\_\-REG}~PMIC0
\item 
\#define {\bf POVEN0\_\-REG}~PMIC0
\item 
\#define {\bf CS10\_\-REG}~TCCR1B
\item 
\#define {\bf CS11\_\-REG}~TCCR1B
\item 
\#define {\bf CS12\_\-REG}~TCCR1B
\item 
\#define {\bf WGM12\_\-REG}~TCCR1B
\item 
\#define {\bf WGM13\_\-REG}~TCCR1B
\item 
\#define {\bf ICES1\_\-REG}~TCCR1B
\item 
\#define {\bf ICNC1\_\-REG}~TCCR1B
\item 
\#define {\bf POEN0A\_\-REG}~POC
\item 
\#define {\bf POEN0B\_\-REG}~POC
\item 
\#define {\bf POEN1A\_\-REG}~POC
\item 
\#define {\bf POEN1B\_\-REG}~POC
\item 
\#define {\bf POEN2A\_\-REG}~POC
\item 
\#define {\bf POEN2B\_\-REG}~POC
\item 
\#define {\bf SPMEN\_\-REG}~SPMCSR
\item 
\#define {\bf PGERS\_\-REG}~SPMCSR
\item 
\#define {\bf PGWRT\_\-REG}~SPMCSR
\item 
\#define {\bf BLBSET\_\-REG}~SPMCSR
\item 
\#define {\bf RWWSRE\_\-REG}~SPMCSR
\item 
\#define {\bf SIGRD\_\-REG}~SPMCSR
\item 
\#define {\bf RWWSB\_\-REG}~SPMCSR
\item 
\#define {\bf SPMIE\_\-REG}~SPMCSR
\item 
\#define {\bf POPA\_\-REG}~PCNF
\item 
\#define {\bf POPB\_\-REG}~PCNF
\item 
\#define {\bf PMODE\_\-REG}~PCNF
\item 
\#define {\bf PULOCK\_\-REG}~PCNF
\item 
\#define {\bf PRS0\_\-REG}~CANBT2
\item 
\#define {\bf PRS1\_\-REG}~CANBT2
\item 
\#define {\bf PRS2\_\-REG}~CANBT2
\item 
\#define {\bf SJW0\_\-REG}~CANBT2
\item 
\#define {\bf SJW1\_\-REG}~CANBT2
\item 
\#define {\bf SMP\_\-REG}~CANBT3
\item 
\#define {\bf PHS10\_\-REG}~CANBT3
\item 
\#define {\bf PHS11\_\-REG}~CANBT3
\item 
\#define {\bf PHS12\_\-REG}~CANBT3
\item 
\#define {\bf PHS20\_\-REG}~CANBT3
\item 
\#define {\bf PHS21\_\-REG}~CANBT3
\item 
\#define {\bf PHS22\_\-REG}~CANBT3
\item 
\#define {\bf ADCL0\_\-REG}~ADCL
\item 
\#define {\bf ADCL1\_\-REG}~ADCL
\item 
\#define {\bf ADCL2\_\-REG}~ADCL
\item 
\#define {\bf ADCL3\_\-REG}~ADCL
\item 
\#define {\bf ADCL4\_\-REG}~ADCL
\item 
\#define {\bf ADCL5\_\-REG}~ADCL
\item 
\#define {\bf ADCL6\_\-REG}~ADCL
\item 
\#define {\bf ADCL7\_\-REG}~ADCL
\item 
\#define {\bf BRP0\_\-REG}~CANBT1
\item 
\#define {\bf BRP1\_\-REG}~CANBT1
\item 
\#define {\bf BRP2\_\-REG}~CANBT1
\item 
\#define {\bf BRP3\_\-REG}~CANBT1
\item 
\#define {\bf BRP4\_\-REG}~CANBT1
\item 
\#define {\bf BRP5\_\-REG}~CANBT1
\item 
\#define {\bf ADCH0\_\-REG}~ADCH
\item 
\#define {\bf ADCH1\_\-REG}~ADCH
\item 
\#define {\bf ADCH2\_\-REG}~ADCH
\item 
\#define {\bf ADCH3\_\-REG}~ADCH
\item 
\#define {\bf ADCH4\_\-REG}~ADCH
\item 
\#define {\bf ADCH5\_\-REG}~ADCH
\item 
\#define {\bf ADCH6\_\-REG}~ADCH
\item 
\#define {\bf ADCH7\_\-REG}~ADCH
\item 
\#define {\bf ADPS0\_\-REG}~ADCSRA
\item 
\#define {\bf ADPS1\_\-REG}~ADCSRA
\item 
\#define {\bf ADPS2\_\-REG}~ADCSRA
\item 
\#define {\bf ADIE\_\-REG}~ADCSRA
\item 
\#define {\bf ADIF\_\-REG}~ADCSRA
\item 
\#define {\bf ADATE\_\-REG}~ADCSRA
\item 
\#define {\bf ADSC\_\-REG}~ADCSRA
\item 
\#define {\bf ADEN\_\-REG}~ADCSRA
\item 
\#define {\bf TOIE0\_\-REG}~TIMSK0
\item 
\#define {\bf OCIE0A\_\-REG}~TIMSK0
\item 
\#define {\bf OCIE0B\_\-REG}~TIMSK0
\item 
\#define {\bf TOIE1\_\-REG}~TIMSK1
\item 
\#define {\bf OCIE1A\_\-REG}~TIMSK1
\item 
\#define {\bf OCIE1B\_\-REG}~TIMSK1
\item 
\#define {\bf ICIE1\_\-REG}~TIMSK1
\item 
\#define {\bf AMP0TS0\_\-REG}~AMP0CSR
\item 
\#define {\bf AMP0TS1\_\-REG}~AMP0CSR
\item 
\#define {\bf AMP0TS2\_\-REG}~AMP0CSR
\item 
\#define {\bf AMPCMP0\_\-REG}~AMP0CSR
\item 
\#define {\bf AMP0G0\_\-REG}~AMP0CSR
\item 
\#define {\bf AMP0G1\_\-REG}~AMP0CSR
\item 
\#define {\bf AMP0IS\_\-REG}~AMP0CSR
\item 
\#define {\bf AMP0EN\_\-REG}~AMP0CSR
\item 
\#define {\bf DAEN\_\-REG}~DACON
\item 
\#define {\bf DALA\_\-REG}~DACON
\item 
\#define {\bf DATS0\_\-REG}~DACON
\item 
\#define {\bf DATS1\_\-REG}~DACON
\item 
\#define {\bf DATS2\_\-REG}~DACON
\item 
\#define {\bf DAATE\_\-REG}~DACON
\item 
\#define {\bf PCINT0\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT1\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT2\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT3\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT4\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT5\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT6\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT7\_\-REG}~PCMSK0
\item 
\#define {\bf PCINT8\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT9\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT10\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT11\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT12\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT13\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT14\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT15\_\-REG}~PCMSK1
\item 
\#define {\bf PCINT16\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT17\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT18\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT19\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT20\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT21\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT22\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT23\_\-REG}~PCMSK2
\item 
\#define {\bf PCINT24\_\-REG}~PCMSK3
\item 
\#define {\bf PCINT25\_\-REG}~PCMSK3
\item 
\#define {\bf PCINT26\_\-REG}~PCMSK3
\item 
\#define {\bf PINC0\_\-REG}~PINC
\item 
\#define {\bf PINC1\_\-REG}~PINC
\item 
\#define {\bf PINC2\_\-REG}~PINC
\item 
\#define {\bf PINC3\_\-REG}~PINC
\item 
\#define {\bf PINC4\_\-REG}~PINC
\item 
\#define {\bf PINC5\_\-REG}~PINC
\item 
\#define {\bf PINC6\_\-REG}~PINC
\item 
\#define {\bf PINC7\_\-REG}~PINC
\item 
\#define {\bf PINB0\_\-REG}~PINB
\item 
\#define {\bf PINB1\_\-REG}~PINB
\item 
\#define {\bf PINB2\_\-REG}~PINB
\item 
\#define {\bf PINB3\_\-REG}~PINB
\item 
\#define {\bf PINB4\_\-REG}~PINB
\item 
\#define {\bf PINB5\_\-REG}~PINB
\item 
\#define {\bf PINB6\_\-REG}~PINB
\item 
\#define {\bf PINB7\_\-REG}~PINB
\item 
\#define {\bf AC0M0\_\-REG}~AC0CON
\item 
\#define {\bf AC0M1\_\-REG}~AC0CON
\item 
\#define {\bf AC0M2\_\-REG}~AC0CON
\item 
\#define {\bf ACCKSEL\_\-REG}~AC0CON
\item 
\#define {\bf AC0IS0\_\-REG}~AC0CON
\item 
\#define {\bf AC0IS1\_\-REG}~AC0CON
\item 
\#define {\bf AC0IE\_\-REG}~AC0CON
\item 
\#define {\bf AC0EN\_\-REG}~AC0CON
\item 
\#define {\bf PINE0\_\-REG}~PINE
\item 
\#define {\bf PINE1\_\-REG}~PINE
\item 
\#define {\bf PINE2\_\-REG}~PINE
\item 
\#define {\bf PIND0\_\-REG}~PIND
\item 
\#define {\bf PIND1\_\-REG}~PIND
\item 
\#define {\bf PIND2\_\-REG}~PIND
\item 
\#define {\bf PIND3\_\-REG}~PIND
\item 
\#define {\bf PIND4\_\-REG}~PIND
\item 
\#define {\bf PIND5\_\-REG}~PIND
\item 
\#define {\bf PIND6\_\-REG}~PIND
\item 
\#define {\bf PIND7\_\-REG}~PIND
\item 
\#define {\bf OCR1AH0\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH1\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH2\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH3\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH4\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH5\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH6\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AH7\_\-REG}~OCR1AH
\item 
\#define {\bf OCR1AL0\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL1\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL2\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL3\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL4\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL5\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL6\_\-REG}~OCR1AL
\item 
\#define {\bf OCR1AL7\_\-REG}~OCR1AL
\item 
\#define {\bf TOV0\_\-REG}~TIFR0
\item 
\#define {\bf OCF0A\_\-REG}~TIFR0
\item 
\#define {\bf OCF0B\_\-REG}~TIFR0
\item 
\#define {\bf POCR0SB\_\-8\_\-REG}~POCR0SBH
\item 
\#define {\bf POCR0SB\_\-9\_\-REG}~POCR0SBH
\item 
\#define {\bf POCR0SB\_\-00\_\-REG}~POCR0SBH
\item 
\#define {\bf POCR0SB\_\-01\_\-REG}~POCR0SBH
\item 
\#define {\bf MISO\_\-PORT}~PORTB
\item 
\#define {\bf MISO\_\-BIT}~0
\item 
\#define {\bf PSCOUT2A\_\-PORT}~PORTB
\item 
\#define {\bf PSCOUT2A\_\-BIT}~0
\item 
\#define {\bf PCINT0\_\-PORT}~PORTB
\item 
\#define {\bf PCINT0\_\-BIT}~0
\item 
\#define {\bf MOSI\_\-PORT}~PORTB
\item 
\#define {\bf MOSI\_\-BIT}~1
\item 
\#define {\bf PSCOUT2B\_\-PORT}~PORTB
\item 
\#define {\bf PSCOUT2B\_\-BIT}~1
\item 
\#define {\bf PCINT1\_\-PORT}~PORTB
\item 
\#define {\bf PCINT1\_\-BIT}~1
\item 
\#define {\bf ADC5\_\-PORT}~PORTB
\item 
\#define {\bf ADC5\_\-BIT}~2
\item 
\#define {\bf INT1\_\-PORT}~PORTB
\item 
\#define {\bf INT1\_\-BIT}~2
\item 
\#define {\bf ACMPN0\_\-PORT}~PORTB
\item 
\#define {\bf ACMPN0\_\-BIT}~2
\item 
\#define {\bf PCINT2\_\-PORT}~PORTB
\item 
\#define {\bf PCINT2\_\-BIT}~2
\item 
\#define {\bf AMP0}~-\_\-PORT PORTB
\item 
\#define {\bf AMP0}~-\_\-BIT 3
\item 
\#define {\bf PCINT3\_\-PORT}~PORTB
\item 
\#define {\bf PCINT3\_\-BIT}~3
\item 
\#define {\bf AMP0}~+\_\-PORT PORTB
\item 
\#define {\bf AMP0}~+\_\-BIT 4
\item 
\#define {\bf PCINT4\_\-PORT}~PORTB
\item 
\#define {\bf PCINT4\_\-BIT}~4
\item 
\#define {\bf ADC6\_\-PORT}~PORTB
\item 
\#define {\bf ADC6\_\-BIT}~5
\item 
\#define {\bf INT2\_\-PORT}~PORTB
\item 
\#define {\bf INT2\_\-BIT}~5
\item 
\#define {\bf ACMPN1\_\-PORT}~PORTB
\item 
\#define {\bf ACMPN1\_\-BIT}~5
\item 
\#define {\bf AMP2}~-\_\-PORT PORTB
\item 
\#define {\bf AMP2}~-\_\-BIT 5
\item 
\#define {\bf PCINT5\_\-PORT}~PORTB
\item 
\#define {\bf PCINT5\_\-BIT}~5
\item 
\#define {\bf ADC7\_\-PORT}~PORTB
\item 
\#define {\bf ADC7\_\-BIT}~6
\item 
\#define {\bf PSCOUT1B\_\-PORT}~PORTB
\item 
\#define {\bf PSCOUT1B\_\-BIT}~6
\item 
\#define {\bf PCINT6\_\-PORT}~PORTB
\item 
\#define {\bf PCINT6\_\-BIT}~6
\item 
\#define {\bf ADC4\_\-PORT}~PORTB
\item 
\#define {\bf ADC4\_\-BIT}~7
\item 
\#define {\bf PSCOUT0B\_\-PORT}~PORTB
\item 
\#define {\bf PSCOUT0B\_\-BIT}~7
\item 
\#define {\bf SCK\_\-PORT}~PORTB
\item 
\#define {\bf SCK\_\-BIT}~7
\item 
\#define {\bf PCINT7\_\-PORT}~PORTB
\item 
\#define {\bf PCINT7\_\-BIT}~7
\item 
\#define {\bf INT3\_\-PORT}~PORTC
\item 
\#define {\bf INT3\_\-BIT}~0
\item 
\#define {\bf PSCOUT1A\_\-PORT}~PORTC
\item 
\#define {\bf PSCOUT1A\_\-BIT}~0
\item 
\#define {\bf PCINT8\_\-PORT}~PORTC
\item 
\#define {\bf PCINT8\_\-BIT}~0
\item 
\#define {\bf PSCIN1\_\-PORT}~PORTC
\item 
\#define {\bf PSCIN1\_\-BIT}~1
\item 
\#define {\bf OC1B\_\-PORT}~PORTC
\item 
\#define {\bf OC1B\_\-BIT}~1
\item 
\#define {\bf SS\_\-A\_\-PORT}~PORTC
\item 
\#define {\bf SS\_\-A\_\-BIT}~1
\item 
\#define {\bf PCINT9\_\-PORT}~PORTC
\item 
\#define {\bf PCINT9\_\-BIT}~1
\item 
\#define {\bf T0\_\-PORT}~PORTC
\item 
\#define {\bf T0\_\-BIT}~2
\item 
\#define {\bf TXCAN\_\-PORT}~PORTC
\item 
\#define {\bf TXCAN\_\-BIT}~2
\item 
\#define {\bf PCINT10\_\-PORT}~PORTC
\item 
\#define {\bf PCINT10\_\-BIT}~2
\item 
\#define {\bf T1\_\-PORT}~PORTC
\item 
\#define {\bf T1\_\-BIT}~3
\item 
\#define {\bf RXCAN\_\-PORT}~PORTC
\item 
\#define {\bf RXCAN\_\-BIT}~3
\item 
\#define {\bf ICP1B\_\-PORT}~PORTC
\item 
\#define {\bf ICP1B\_\-BIT}~3
\item 
\#define {\bf PCINT11\_\-PORT}~PORTC
\item 
\#define {\bf PCINT11\_\-BIT}~3
\item 
\#define {\bf ADC8\_\-PORT}~PORTC
\item 
\#define {\bf ADC8\_\-BIT}~4
\item 
\#define {\bf AMP1}~-\_\-PORT PORTC
\item 
\#define {\bf AMP1}~-\_\-BIT 4
\item 
\#define {\bf ACMPN3\_\-PORT}~PORTC
\item 
\#define {\bf ACMPN3\_\-BIT}~4
\item 
\#define {\bf PCINT12\_\-PORT}~PORTC
\item 
\#define {\bf PCINT12\_\-BIT}~4
\item 
\#define {\bf ADC9\_\-PORT}~PORTC
\item 
\#define {\bf ADC9\_\-BIT}~5
\item 
\#define {\bf AMP1}~+\_\-PORT PORTC
\item 
\#define {\bf AMP1}~+\_\-BIT 5
\item 
\#define {\bf ACMP3\_\-PORT}~PORTC
\item 
\#define {\bf ACMP3\_\-BIT}~5
\item 
\#define {\bf PCINT13\_\-PORT}~PORTC
\item 
\#define {\bf PCINT13\_\-BIT}~5
\item 
\#define {\bf ADC10\_\-PORT}~PORTC
\item 
\#define {\bf ADC10\_\-BIT}~6
\item 
\#define {\bf ACMP1\_\-PORT}~PORTC
\item 
\#define {\bf ACMP1\_\-BIT}~6
\item 
\#define {\bf PCINT14\_\-PORT}~PORTC
\item 
\#define {\bf PCINT14\_\-BIT}~6
\item 
\#define {\bf D2A\_\-PORT}~PORTC
\item 
\#define {\bf D2A\_\-BIT}~7
\item 
\#define {\bf AMP2}~+\_\-PORT PORTC
\item 
\#define {\bf AMP2}~+\_\-BIT 7
\item 
\#define {\bf PCINT15\_\-PORT}~PORTC
\item 
\#define {\bf PCINT15\_\-BIT}~7
\item 
\#define {\bf PSCOUT0A\_\-PORT}~PORTD
\item 
\#define {\bf PSCOUT0A\_\-BIT}~0
\item 
\#define {\bf PCINT16\_\-PORT}~PORTD
\item 
\#define {\bf PCINT16\_\-BIT}~0
\item 
\#define {\bf PSCIN0\_\-PORT}~PORTD
\item 
\#define {\bf PSCIN0\_\-BIT}~1
\item 
\#define {\bf CLK0\_\-PORT}~PORTD
\item 
\#define {\bf CLK0\_\-BIT}~1
\item 
\#define {\bf PCINT17\_\-PORT}~PORTD
\item 
\#define {\bf PCINT17\_\-BIT}~1
\item 
\#define {\bf PSCIN2\_\-PORT}~PORTD
\item 
\#define {\bf PSCIN2\_\-BIT}~2
\item 
\#define {\bf OC1A\_\-PORT}~PORTD
\item 
\#define {\bf OC1A\_\-BIT}~2
\item 
\#define {\bf MISO\_\-A\_\-PORT}~PORTD
\item 
\#define {\bf MISO\_\-A\_\-BIT}~2
\item 
\#define {\bf PCINT18\_\-PORT}~PORTD
\item 
\#define {\bf PCINT18\_\-BIT}~2
\item 
\#define {\bf TXD\_\-PORT}~PORTD
\item 
\#define {\bf TXD\_\-BIT}~3
\item 
\#define {\bf TXLIN\_\-PORT}~PORTD
\item 
\#define {\bf TXLIN\_\-BIT}~3
\item 
\#define {\bf OC0A\_\-PORT}~PORTD
\item 
\#define {\bf OC0A\_\-BIT}~3
\item 
\#define {\bf SS\_\-PORT}~PORTD
\item 
\#define {\bf SS\_\-BIT}~3
\item 
\#define {\bf MOSI\_\-A\_\-PORT}~PORTD
\item 
\#define {\bf MOSI\_\-A\_\-BIT}~3
\item 
\#define {\bf PCINT19\_\-PORT}~PORTD
\item 
\#define {\bf PCINT19\_\-BIT}~3
\item 
\#define {\bf ADC1\_\-PORT}~PORTD
\item 
\#define {\bf ADC1\_\-BIT}~4
\item 
\#define {\bf RXD\_\-PORT}~PORTD
\item 
\#define {\bf RXD\_\-BIT}~4
\item 
\#define {\bf RXLIN\_\-PORT}~PORTD
\item 
\#define {\bf RXLIN\_\-BIT}~4
\item 
\#define {\bf ICP1A\_\-PORT}~PORTD
\item 
\#define {\bf ICP1A\_\-BIT}~4
\item 
\#define {\bf SCK\_\-A\_\-PORT}~PORTD
\item 
\#define {\bf SCK\_\-A\_\-BIT}~4
\item 
\#define {\bf PCINT20\_\-PORT}~PORTD
\item 
\#define {\bf PCINT20\_\-BIT}~4
\item 
\#define {\bf ADC2\_\-PORT}~PORTD
\item 
\#define {\bf ADC2\_\-BIT}~5
\item 
\#define {\bf ACMP2\_\-PORT}~PORTD
\item 
\#define {\bf ACMP2\_\-BIT}~5
\item 
\#define {\bf PCINT21\_\-PORT}~PORTD
\item 
\#define {\bf PCINT21\_\-BIT}~5
\item 
\#define {\bf ADC3\_\-PORT}~PORTD
\item 
\#define {\bf ADC3\_\-BIT}~6
\item 
\#define {\bf ACMPN2\_\-PORT}~PORTD
\item 
\#define {\bf ACMPN2\_\-BIT}~6
\item 
\#define {\bf INT0\_\-PORT}~PORTD
\item 
\#define {\bf INT0\_\-BIT}~6
\item 
\#define {\bf PCINT22\_\-PORT}~PORTD
\item 
\#define {\bf PCINT22\_\-BIT}~6
\item 
\#define {\bf ACMP0\_\-PORT}~PORTD
\item 
\#define {\bf ACMP0\_\-BIT}~7
\item 
\#define {\bf PCINT23\_\-PORT}~PORTD
\item 
\#define {\bf PCINT23\_\-BIT}~7
\item 
\#define {\bf RESET\_\-PORT}~PORTE
\item 
\#define {\bf RESET\_\-BIT}~0
\item 
\#define {\bf OCD\_\-PORT}~PORTE
\item 
\#define {\bf OCD\_\-BIT}~0
\item 
\#define {\bf PCINT24\_\-PORT}~PORTE
\item 
\#define {\bf PCINT24\_\-BIT}~0
\item 
\#define {\bf OC0B\_\-PORT}~PORTE
\item 
\#define {\bf OC0B\_\-BIT}~1
\item 
\#define {\bf XTAL1\_\-PORT}~PORTE
\item 
\#define {\bf XTAL1\_\-BIT}~1
\item 
\#define {\bf PCINT25\_\-PORT}~PORTE
\item 
\#define {\bf PCINT25\_\-BIT}~1
\item 
\#define {\bf ADC0\_\-PORT}~PORTE
\item 
\#define {\bf ADC0\_\-BIT}~2
\item 
\#define {\bf XTAL2\_\-PORT}~PORTE
\item 
\#define {\bf XTAL2\_\-BIT}~2
\item 
\#define {\bf PCINT26\_\-PORT}~PORTE
\item 
\#define {\bf PCINT26\_\-BIT}~2
\end{CompactItemize}


\subsection{Define Documentation}
\index{ATmega32M1.h@{ATmega32M1.h}!ABRQ\_\-REG@{ABRQ\_\-REG}}
\index{ABRQ\_\-REG@{ABRQ\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ABRQ\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ABRQ\_\-REG~CANGCON}\label{ATmega32M1_8h_0643dddebada44fcbbaa50eadbe778ac}




Definition at line 301 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0EN\_\-REG@{AC0EN\_\-REG}}
\index{AC0EN\_\-REG@{AC0EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0EN\_\-REG~AC0CON}\label{ATmega32M1_8h_dd3817b614896721a415d1aeed377b6a}




Definition at line 1291 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0IE\_\-REG@{AC0IE\_\-REG}}
\index{AC0IE\_\-REG@{AC0IE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0IE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0IE\_\-REG~AC0CON}\label{ATmega32M1_8h_6f2f6b7ca81ba11a606c8d1959adacdc}




Definition at line 1290 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0IF\_\-REG@{AC0IF\_\-REG}}
\index{AC0IF\_\-REG@{AC0IF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0IF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0IF\_\-REG~ACSR}\label{ATmega32M1_8h_4d33d3e2fea3215e0b9a048eb58d5deb}




Definition at line 1087 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0IS0\_\-REG@{AC0IS0\_\-REG}}
\index{AC0IS0\_\-REG@{AC0IS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0IS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0IS0\_\-REG~AC0CON}\label{ATmega32M1_8h_a06386cd8a559408408f0acf77539ad3}




Definition at line 1288 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0IS1\_\-REG@{AC0IS1\_\-REG}}
\index{AC0IS1\_\-REG@{AC0IS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0IS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0IS1\_\-REG~AC0CON}\label{ATmega32M1_8h_8da1830e1668f153bfa55aab52eefc2a}




Definition at line 1289 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0M0\_\-REG@{AC0M0\_\-REG}}
\index{AC0M0\_\-REG@{AC0M0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0M0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0M0\_\-REG~AC0CON}\label{ATmega32M1_8h_201cb13c15ea1e3c22b6f2c2e1cadf16}




Definition at line 1284 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0M1\_\-REG@{AC0M1\_\-REG}}
\index{AC0M1\_\-REG@{AC0M1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0M1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0M1\_\-REG~AC0CON}\label{ATmega32M1_8h_043da72b2f7f2efea0d3460acfd4201a}




Definition at line 1285 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0M2\_\-REG@{AC0M2\_\-REG}}
\index{AC0M2\_\-REG@{AC0M2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0M2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0M2\_\-REG~AC0CON}\label{ATmega32M1_8h_606b605114dd0eef0b4a73400a0dc549}




Definition at line 1286 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC0O\_\-REG@{AC0O\_\-REG}}
\index{AC0O\_\-REG@{AC0O\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC0O\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC0O\_\-REG~ACSR}\label{ATmega32M1_8h_bd6f1b8e1ee21cdfc2ed451b90327ce3}




Definition at line 1083 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1EN\_\-REG@{AC1EN\_\-REG}}
\index{AC1EN\_\-REG@{AC1EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1EN\_\-REG~AC1CON}\label{ATmega32M1_8h_eceac62bfce33fd1807edf692fd2b8a7}




Definition at line 244 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1ICE\_\-REG@{AC1ICE\_\-REG}}
\index{AC1ICE\_\-REG@{AC1ICE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1ICE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1ICE\_\-REG~AC1CON}\label{ATmega32M1_8h_4bda64361327186a0515430a12824cfc}




Definition at line 240 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1IE\_\-REG@{AC1IE\_\-REG}}
\index{AC1IE\_\-REG@{AC1IE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1IE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1IE\_\-REG~AC1CON}\label{ATmega32M1_8h_25feae89379d0b0383f66e07548c7236}




Definition at line 243 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1IF\_\-REG@{AC1IF\_\-REG}}
\index{AC1IF\_\-REG@{AC1IF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1IF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1IF\_\-REG~ACSR}\label{ATmega32M1_8h_b6ccc5beb5e8ee9be07f03224ff09717}




Definition at line 1088 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1IS0\_\-REG@{AC1IS0\_\-REG}}
\index{AC1IS0\_\-REG@{AC1IS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1IS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1IS0\_\-REG~AC1CON}\label{ATmega32M1_8h_9c4179a27b60e33c9f0c49b732403551}




Definition at line 241 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1IS1\_\-REG@{AC1IS1\_\-REG}}
\index{AC1IS1\_\-REG@{AC1IS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1IS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1IS1\_\-REG~AC1CON}\label{ATmega32M1_8h_a738856ab59442aabe22d4485a05938a}




Definition at line 242 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1M0\_\-REG@{AC1M0\_\-REG}}
\index{AC1M0\_\-REG@{AC1M0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1M0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1M0\_\-REG~AC1CON}\label{ATmega32M1_8h_a6d354b02b5a0d9a498f3ac14e43cab2}




Definition at line 237 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1M1\_\-REG@{AC1M1\_\-REG}}
\index{AC1M1\_\-REG@{AC1M1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1M1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1M1\_\-REG~AC1CON}\label{ATmega32M1_8h_36fbdce06e077c95ae9315a891faabfa}




Definition at line 238 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1M2\_\-REG@{AC1M2\_\-REG}}
\index{AC1M2\_\-REG@{AC1M2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1M2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1M2\_\-REG~AC1CON}\label{ATmega32M1_8h_89b734c76bdf5586e1fbacbf097d2a13}




Definition at line 239 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC1O\_\-REG@{AC1O\_\-REG}}
\index{AC1O\_\-REG@{AC1O\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC1O\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC1O\_\-REG~ACSR}\label{ATmega32M1_8h_d4d3127123a6f3d7a16303338f2c6d78}




Definition at line 1084 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2EN\_\-REG@{AC2EN\_\-REG}}
\index{AC2EN\_\-REG@{AC2EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2EN\_\-REG~AC2CON}\label{ATmega32M1_8h_c8b1cee237e70fa4e49934f25060a03f}




Definition at line 355 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2IE\_\-REG@{AC2IE\_\-REG}}
\index{AC2IE\_\-REG@{AC2IE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2IE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2IE\_\-REG~AC2CON}\label{ATmega32M1_8h_e87c3c8b4a11762d7cb8ebeac1b02d1d}




Definition at line 354 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2IF\_\-REG@{AC2IF\_\-REG}}
\index{AC2IF\_\-REG@{AC2IF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2IF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2IF\_\-REG~ACSR}\label{ATmega32M1_8h_a5080608d92d3dd7545068e2f68acad4}




Definition at line 1089 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2IS0\_\-REG@{AC2IS0\_\-REG}}
\index{AC2IS0\_\-REG@{AC2IS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2IS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2IS0\_\-REG~AC2CON}\label{ATmega32M1_8h_6cd52fbbf5f3c201d82a5af0e81b342c}




Definition at line 352 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2IS1\_\-REG@{AC2IS1\_\-REG}}
\index{AC2IS1\_\-REG@{AC2IS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2IS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2IS1\_\-REG~AC2CON}\label{ATmega32M1_8h_480b1d04fbea2925a7ad629cf21ae1fa}




Definition at line 353 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2M0\_\-REG@{AC2M0\_\-REG}}
\index{AC2M0\_\-REG@{AC2M0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2M0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2M0\_\-REG~AC2CON}\label{ATmega32M1_8h_ae06f05ad0cb0dda9c883ce1941e5941}




Definition at line 349 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2M1\_\-REG@{AC2M1\_\-REG}}
\index{AC2M1\_\-REG@{AC2M1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2M1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2M1\_\-REG~AC2CON}\label{ATmega32M1_8h_2fd8adc582a51a950b5d5e1c51557d1e}




Definition at line 350 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2M2\_\-REG@{AC2M2\_\-REG}}
\index{AC2M2\_\-REG@{AC2M2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2M2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2M2\_\-REG~AC2CON}\label{ATmega32M1_8h_2699eaf0442dc2a8b96c0a09194b7669}




Definition at line 351 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC2O\_\-REG@{AC2O\_\-REG}}
\index{AC2O\_\-REG@{AC2O\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC2O\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC2O\_\-REG~ACSR}\label{ATmega32M1_8h_52ad01603ea2313f100a1c61394cb400}




Definition at line 1085 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3EN\_\-REG@{AC3EN\_\-REG}}
\index{AC3EN\_\-REG@{AC3EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3EN\_\-REG~AC3CON}\label{ATmega32M1_8h_276deedea9d0dd7cd5620d51bdc285ec}




Definition at line 603 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3IE\_\-REG@{AC3IE\_\-REG}}
\index{AC3IE\_\-REG@{AC3IE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3IE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3IE\_\-REG~AC3CON}\label{ATmega32M1_8h_cd646a50c658b44ebd9839d3d02ead5f}




Definition at line 602 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3IF\_\-REG@{AC3IF\_\-REG}}
\index{AC3IF\_\-REG@{AC3IF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3IF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3IF\_\-REG~ACSR}\label{ATmega32M1_8h_7535129af5e11a1e066a5f7280621ba8}




Definition at line 1090 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3IS0\_\-REG@{AC3IS0\_\-REG}}
\index{AC3IS0\_\-REG@{AC3IS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3IS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3IS0\_\-REG~AC3CON}\label{ATmega32M1_8h_c23f152483aa753aeb32db585d8fb37a}




Definition at line 600 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3IS1\_\-REG@{AC3IS1\_\-REG}}
\index{AC3IS1\_\-REG@{AC3IS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3IS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3IS1\_\-REG~AC3CON}\label{ATmega32M1_8h_20c1168b80514322938d48a33083a76e}




Definition at line 601 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3M0\_\-REG@{AC3M0\_\-REG}}
\index{AC3M0\_\-REG@{AC3M0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3M0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3M0\_\-REG~AC3CON}\label{ATmega32M1_8h_a9815833d48829bb8ca963aedc0abc32}




Definition at line 597 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3M1\_\-REG@{AC3M1\_\-REG}}
\index{AC3M1\_\-REG@{AC3M1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3M1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3M1\_\-REG~AC3CON}\label{ATmega32M1_8h_1611cf8938f039868988db43d5e8b693}




Definition at line 598 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3M2\_\-REG@{AC3M2\_\-REG}}
\index{AC3M2\_\-REG@{AC3M2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3M2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3M2\_\-REG~AC3CON}\label{ATmega32M1_8h_3c436f90f864f45a06ca5529556e9a89}




Definition at line 599 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AC3O\_\-REG@{AC3O\_\-REG}}
\index{AC3O\_\-REG@{AC3O\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AC3O\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AC3O\_\-REG~ACSR}\label{ATmega32M1_8h_5ae65b77d9a32f27d785fb6cc77324d8}




Definition at line 1086 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACCKSEL\_\-REG@{ACCKSEL\_\-REG}}
\index{ACCKSEL\_\-REG@{ACCKSEL\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACCKSEL\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ACCKSEL\_\-REG~AC0CON}\label{ATmega32M1_8h_21c89a0ec18748bd2744f5452abaf707}




Definition at line 1287 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP0\_\-BIT@{ACMP0\_\-BIT}}
\index{ACMP0\_\-BIT@{ACMP0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP0\_\-BIT~7}\label{ATmega32M1_8h_587e28a132cdd38259b878c49224c307}




Definition at line 1528 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP0\_\-PORT@{ACMP0\_\-PORT}}
\index{ACMP0\_\-PORT@{ACMP0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP0\_\-PORT~PORTD}\label{ATmega32M1_8h_98372be7e9c9b5f894c38e60694e613d}




Definition at line 1527 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP0D\_\-REG@{ACMP0D\_\-REG}}
\index{ACMP0D\_\-REG@{ACMP0D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP0D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP0D\_\-REG~DIDR1}\label{ATmega32M1_8h_b423c2e3018790bd36d4f116302f98ec}




Definition at line 415 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP1\_\-BIT@{ACMP1\_\-BIT}}
\index{ACMP1\_\-BIT@{ACMP1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP1\_\-BIT~6}\label{ATmega32M1_8h_bebeaa6ce953ace01972855ab632be1e}




Definition at line 1453 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP1\_\-PORT@{ACMP1\_\-PORT}}
\index{ACMP1\_\-PORT@{ACMP1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP1\_\-PORT~PORTC}\label{ATmega32M1_8h_56159120e23ab67066eaf5262daa1149}




Definition at line 1452 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP2\_\-BIT@{ACMP2\_\-BIT}}
\index{ACMP2\_\-BIT@{ACMP2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP2\_\-BIT~5}\label{ATmega32M1_8h_940c69ec688d8846969bd54c23a87299}




Definition at line 1514 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP2\_\-PORT@{ACMP2\_\-PORT}}
\index{ACMP2\_\-PORT@{ACMP2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP2\_\-PORT~PORTD}\label{ATmega32M1_8h_86d97421430b45d6ff01305af75460b4}




Definition at line 1513 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP3\_\-BIT@{ACMP3\_\-BIT}}
\index{ACMP3\_\-BIT@{ACMP3\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP3\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP3\_\-BIT~5}\label{ATmega32M1_8h_9249d07b368d3c060519e842d07f4353}




Definition at line 1446 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMP3\_\-PORT@{ACMP3\_\-PORT}}
\index{ACMP3\_\-PORT@{ACMP3\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMP3\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMP3\_\-PORT~PORTC}\label{ATmega32M1_8h_03f175a10e44ef5303dcc1fccccd85bd}




Definition at line 1445 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN0\_\-BIT@{ACMPN0\_\-BIT}}
\index{ACMPN0\_\-BIT@{ACMPN0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN0\_\-BIT~2}\label{ATmega32M1_8h_7fabbb4ef73b47f8e037aaf1be266d21}




Definition at line 1359 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN0\_\-PORT@{ACMPN0\_\-PORT}}
\index{ACMPN0\_\-PORT@{ACMPN0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN0\_\-PORT~PORTB}\label{ATmega32M1_8h_4387a2e49e3da11d03cc62c15d276ea5}




Definition at line 1358 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN1\_\-BIT@{ACMPN1\_\-BIT}}
\index{ACMPN1\_\-BIT@{ACMPN1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN1\_\-BIT~5}\label{ATmega32M1_8h_11ee56a3fc0609c4089834aec7f69aa4}




Definition at line 1378 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN1\_\-PORT@{ACMPN1\_\-PORT}}
\index{ACMPN1\_\-PORT@{ACMPN1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN1\_\-PORT~PORTB}\label{ATmega32M1_8h_49ab811e095dfc8225de472fffae0a10}




Definition at line 1377 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN2\_\-BIT@{ACMPN2\_\-BIT}}
\index{ACMPN2\_\-BIT@{ACMPN2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN2\_\-BIT~6}\label{ATmega32M1_8h_a45479b630573c134033b01c6ca80bad}




Definition at line 1521 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN2\_\-PORT@{ACMPN2\_\-PORT}}
\index{ACMPN2\_\-PORT@{ACMPN2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN2\_\-PORT~PORTD}\label{ATmega32M1_8h_a2fa9047d6d15622bbfa4edc388b11c7}




Definition at line 1520 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN3\_\-BIT@{ACMPN3\_\-BIT}}
\index{ACMPN3\_\-BIT@{ACMPN3\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN3\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN3\_\-BIT~4}\label{ATmega32M1_8h_def831cc6f58b87b9a0420063efaa27f}




Definition at line 1437 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ACMPN3\_\-PORT@{ACMPN3\_\-PORT}}
\index{ACMPN3\_\-PORT@{ACMPN3\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ACMPN3\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ACMPN3\_\-PORT~PORTC}\label{ATmega32M1_8h_3be90d405f6d4cf28fb4eba8ffb8ab22}




Definition at line 1436 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADATE\_\-REG@{ADATE\_\-REG}}
\index{ADATE\_\-REG@{ADATE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADATE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADATE\_\-REG~ADCSRA}\label{ATmega32M1_8h_1ce6529af5065fe4c63f88d08ec3aea1}




Definition at line 1195 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC0\_\-BIT@{ADC0\_\-BIT}}
\index{ADC0\_\-BIT@{ADC0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC0\_\-BIT~2}\label{ATmega32M1_8h_7206c4bd8a6f4a826f3335983cd2f20a}




Definition at line 1547 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC0\_\-PORT@{ADC0\_\-PORT}}
\index{ADC0\_\-PORT@{ADC0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC0\_\-PORT~PORTE}\label{ATmega32M1_8h_030fbd74b964f9c0046a74f46a42276b}




Definition at line 1546 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC0D\_\-REG@{ADC0D\_\-REG}}
\index{ADC0D\_\-REG@{ADC0D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC0D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC0D\_\-REG~DIDR0}\label{ATmega32M1_8h_929eba87ade35b10be03793169858344}




Definition at line 400 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC10\_\-BIT@{ADC10\_\-BIT}}
\index{ADC10\_\-BIT@{ADC10\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC10\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC10\_\-BIT~6}\label{ATmega32M1_8h_915de022cabd16e4451074bdbf24a19f}




Definition at line 1451 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC10\_\-PORT@{ADC10\_\-PORT}}
\index{ADC10\_\-PORT@{ADC10\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC10\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC10\_\-PORT~PORTC}\label{ATmega32M1_8h_0de7b3150d963b9da27b889a4a21f4d8}




Definition at line 1450 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC10D\_\-REG@{ADC10D\_\-REG}}
\index{ADC10D\_\-REG@{ADC10D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC10D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC10D\_\-REG~DIDR1}\label{ATmega32M1_8h_79c6cb4ddc6b09719f337c3d30919ff4}




Definition at line 412 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC1\_\-BIT@{ADC1\_\-BIT}}
\index{ADC1\_\-BIT@{ADC1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC1\_\-BIT~4}\label{ATmega32M1_8h_e40ddcc3aacadf79ae2deb704f36a98e}




Definition at line 1499 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC1\_\-PORT@{ADC1\_\-PORT}}
\index{ADC1\_\-PORT@{ADC1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC1\_\-PORT~PORTD}\label{ATmega32M1_8h_a6c3631acac5f073bdc845e9163bc14e}




Definition at line 1498 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC1D\_\-REG@{ADC1D\_\-REG}}
\index{ADC1D\_\-REG@{ADC1D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC1D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC1D\_\-REG~DIDR0}\label{ATmega32M1_8h_bb7da425a267471d02b23a0666084e91}




Definition at line 401 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC2\_\-BIT@{ADC2\_\-BIT}}
\index{ADC2\_\-BIT@{ADC2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC2\_\-BIT~5}\label{ATmega32M1_8h_89fb449e9a1d85f77b89c966a0557fc0}




Definition at line 1512 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC2\_\-PORT@{ADC2\_\-PORT}}
\index{ADC2\_\-PORT@{ADC2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC2\_\-PORT~PORTD}\label{ATmega32M1_8h_e922961d5006c209ce0dc927418f3a8c}




Definition at line 1511 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC2D\_\-REG@{ADC2D\_\-REG}}
\index{ADC2D\_\-REG@{ADC2D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC2D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC2D\_\-REG~DIDR0}\label{ATmega32M1_8h_bb227b9bf9ecc7988c629595978b5a6f}




Definition at line 402 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC3\_\-BIT@{ADC3\_\-BIT}}
\index{ADC3\_\-BIT@{ADC3\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC3\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC3\_\-BIT~6}\label{ATmega32M1_8h_402e4e450020f46ebfcacc50160229de}




Definition at line 1519 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC3\_\-PORT@{ADC3\_\-PORT}}
\index{ADC3\_\-PORT@{ADC3\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC3\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC3\_\-PORT~PORTD}\label{ATmega32M1_8h_4dc2e1861decdb9984d788cdfce21363}




Definition at line 1518 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC3D\_\-REG@{ADC3D\_\-REG}}
\index{ADC3D\_\-REG@{ADC3D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC3D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC3D\_\-REG~DIDR0}\label{ATmega32M1_8h_d8f00f9cc8070f736188ab4cae47c128}




Definition at line 403 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC4\_\-BIT@{ADC4\_\-BIT}}
\index{ADC4\_\-BIT@{ADC4\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC4\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC4\_\-BIT~7}\label{ATmega32M1_8h_c9da02f14e6beba592e365d8f0d11e1c}




Definition at line 1392 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC4\_\-PORT@{ADC4\_\-PORT}}
\index{ADC4\_\-PORT@{ADC4\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC4\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC4\_\-PORT~PORTB}\label{ATmega32M1_8h_1bd33c991b2d830d62695ab6d22f0b4d}




Definition at line 1391 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC4D\_\-REG@{ADC4D\_\-REG}}
\index{ADC4D\_\-REG@{ADC4D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC4D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC4D\_\-REG~DIDR0}\label{ATmega32M1_8h_a832b0af1225c88e52af58ea5de522ba}




Definition at line 404 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC5\_\-BIT@{ADC5\_\-BIT}}
\index{ADC5\_\-BIT@{ADC5\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC5\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC5\_\-BIT~2}\label{ATmega32M1_8h_6175ae8b641ad3c1185cc11feebd46fb}




Definition at line 1355 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC5\_\-PORT@{ADC5\_\-PORT}}
\index{ADC5\_\-PORT@{ADC5\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC5\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC5\_\-PORT~PORTB}\label{ATmega32M1_8h_15f328ff7ab85f171ac83eca2cd85f04}




Definition at line 1354 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC5D\_\-REG@{ADC5D\_\-REG}}
\index{ADC5D\_\-REG@{ADC5D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC5D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC5D\_\-REG~DIDR0}\label{ATmega32M1_8h_47834f0392ea57ffa6fe486c1bccb70a}




Definition at line 405 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC6\_\-BIT@{ADC6\_\-BIT}}
\index{ADC6\_\-BIT@{ADC6\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC6\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC6\_\-BIT~5}\label{ATmega32M1_8h_f70480392e1a476a315f5902616e6be2}




Definition at line 1374 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC6\_\-PORT@{ADC6\_\-PORT}}
\index{ADC6\_\-PORT@{ADC6\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC6\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC6\_\-PORT~PORTB}\label{ATmega32M1_8h_5de855ced29839a6d81eb8c74737ab46}




Definition at line 1373 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC6D\_\-REG@{ADC6D\_\-REG}}
\index{ADC6D\_\-REG@{ADC6D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC6D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC6D\_\-REG~DIDR0}\label{ATmega32M1_8h_c6bd558b9c55dfb53b6de2cabee1d59d}




Definition at line 406 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC7\_\-BIT@{ADC7\_\-BIT}}
\index{ADC7\_\-BIT@{ADC7\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC7\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC7\_\-BIT~6}\label{ATmega32M1_8h_92a6c82a25dac9bbf299287e5ea50b87}




Definition at line 1385 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC7\_\-PORT@{ADC7\_\-PORT}}
\index{ADC7\_\-PORT@{ADC7\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC7\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC7\_\-PORT~PORTB}\label{ATmega32M1_8h_89eb8fcca49d4ac5f9d45b2c7f514e1b}




Definition at line 1384 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC7D\_\-REG@{ADC7D\_\-REG}}
\index{ADC7D\_\-REG@{ADC7D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC7D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC7D\_\-REG~DIDR0}\label{ATmega32M1_8h_ad2da87cf6b8b0390ba5483764dfbeb6}




Definition at line 407 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC8\_\-BIT@{ADC8\_\-BIT}}
\index{ADC8\_\-BIT@{ADC8\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC8\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC8\_\-BIT~4}\label{ATmega32M1_8h_d244d8ad9e37435572ff0c0424c6f1d1}




Definition at line 1433 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC8\_\-PORT@{ADC8\_\-PORT}}
\index{ADC8\_\-PORT@{ADC8\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC8\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC8\_\-PORT~PORTC}\label{ATmega32M1_8h_807ef34d3f312a5d1716eff472a9081a}




Definition at line 1432 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC8D\_\-REG@{ADC8D\_\-REG}}
\index{ADC8D\_\-REG@{ADC8D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC8D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC8D\_\-REG~DIDR1}\label{ATmega32M1_8h_e58454418b7f98f8bfe36d7d923b8725}




Definition at line 410 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC9\_\-BIT@{ADC9\_\-BIT}}
\index{ADC9\_\-BIT@{ADC9\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC9\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC9\_\-BIT~5}\label{ATmega32M1_8h_3a285760ce710c2800e78b02cdb9b0d7}




Definition at line 1442 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC9\_\-PORT@{ADC9\_\-PORT}}
\index{ADC9\_\-PORT@{ADC9\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC9\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC9\_\-PORT~PORTC}\label{ATmega32M1_8h_1e16b151b890780906fbb2aaaaa29a93}




Definition at line 1441 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADC9D\_\-REG@{ADC9D\_\-REG}}
\index{ADC9D\_\-REG@{ADC9D\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADC9D\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADC9D\_\-REG~DIDR1}\label{ATmega32M1_8h_f3647783fa158f9b1905c7427a430789}




Definition at line 411 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH0\_\-REG@{ADCH0\_\-REG}}
\index{ADCH0\_\-REG@{ADCH0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH0\_\-REG~ADCH}\label{ATmega32M1_8h_5b4a5f6024b91f0ec343f6b2e28f0ba6}




Definition at line 1180 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH1\_\-REG@{ADCH1\_\-REG}}
\index{ADCH1\_\-REG@{ADCH1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH1\_\-REG~ADCH}\label{ATmega32M1_8h_bf915e15db6714adb7dbf30cd63b6f0c}




Definition at line 1181 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH2\_\-REG@{ADCH2\_\-REG}}
\index{ADCH2\_\-REG@{ADCH2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH2\_\-REG~ADCH}\label{ATmega32M1_8h_4d75afb271266da893791ef991a108b4}




Definition at line 1182 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH3\_\-REG@{ADCH3\_\-REG}}
\index{ADCH3\_\-REG@{ADCH3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH3\_\-REG~ADCH}\label{ATmega32M1_8h_af8e04ade90d20cb72b7e043734177b9}




Definition at line 1183 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH4\_\-REG@{ADCH4\_\-REG}}
\index{ADCH4\_\-REG@{ADCH4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH4\_\-REG~ADCH}\label{ATmega32M1_8h_b4013206721afd63faf57fcbe67f6bcd}




Definition at line 1184 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH5\_\-REG@{ADCH5\_\-REG}}
\index{ADCH5\_\-REG@{ADCH5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH5\_\-REG~ADCH}\label{ATmega32M1_8h_8a64d9461abc8d9d02cc38ec92d7f333}




Definition at line 1185 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH6\_\-REG@{ADCH6\_\-REG}}
\index{ADCH6\_\-REG@{ADCH6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH6\_\-REG~ADCH}\label{ATmega32M1_8h_b6bb3e6113ecddd0296e8b9490c30186}




Definition at line 1186 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCH7\_\-REG@{ADCH7\_\-REG}}
\index{ADCH7\_\-REG@{ADCH7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCH7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCH7\_\-REG~ADCH}\label{ATmega32M1_8h_f42554f76f11098e469ff92cf84fe35d}




Definition at line 1187 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL0\_\-REG@{ADCL0\_\-REG}}
\index{ADCL0\_\-REG@{ADCL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL0\_\-REG~ADCL}\label{ATmega32M1_8h_4206f6448b830448d3e777cfcea62298}




Definition at line 1162 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL1\_\-REG@{ADCL1\_\-REG}}
\index{ADCL1\_\-REG@{ADCL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL1\_\-REG~ADCL}\label{ATmega32M1_8h_6543c4a466b132fdacee1a80b25b482e}




Definition at line 1163 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL2\_\-REG@{ADCL2\_\-REG}}
\index{ADCL2\_\-REG@{ADCL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL2\_\-REG~ADCL}\label{ATmega32M1_8h_0e464d414b6ab147352499a3ede100b7}




Definition at line 1164 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL3\_\-REG@{ADCL3\_\-REG}}
\index{ADCL3\_\-REG@{ADCL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL3\_\-REG~ADCL}\label{ATmega32M1_8h_2f4c239bef5b88863ccad95757b072e7}




Definition at line 1165 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL4\_\-REG@{ADCL4\_\-REG}}
\index{ADCL4\_\-REG@{ADCL4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL4\_\-REG~ADCL}\label{ATmega32M1_8h_23027c916c7edcadd554b4568d7eec64}




Definition at line 1166 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL5\_\-REG@{ADCL5\_\-REG}}
\index{ADCL5\_\-REG@{ADCL5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL5\_\-REG~ADCL}\label{ATmega32M1_8h_dfccebee254878c9527cced15370511e}




Definition at line 1167 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL6\_\-REG@{ADCL6\_\-REG}}
\index{ADCL6\_\-REG@{ADCL6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL6\_\-REG~ADCL}\label{ATmega32M1_8h_72d0c56ddf4a26025a8f12b58cffe90e}




Definition at line 1168 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADCL7\_\-REG@{ADCL7\_\-REG}}
\index{ADCL7\_\-REG@{ADCL7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADCL7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADCL7\_\-REG~ADCL}\label{ATmega32M1_8h_3b66afa45275ba53254fbf51f624d60f}




Definition at line 1169 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADEN\_\-REG@{ADEN\_\-REG}}
\index{ADEN\_\-REG@{ADEN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADEN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADEN\_\-REG~ADCSRA}\label{ATmega32M1_8h_894e5779251d51319275bdb299b088d9}




Definition at line 1197 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADHSM\_\-REG@{ADHSM\_\-REG}}
\index{ADHSM\_\-REG@{ADHSM\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADHSM\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADHSM\_\-REG~ADCSRB}\label{ATmega32M1_8h_65424362b39a9873610dd9813599cc75}




Definition at line 1052 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADIE\_\-REG@{ADIE\_\-REG}}
\index{ADIE\_\-REG@{ADIE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADIE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADIE\_\-REG~ADCSRA}\label{ATmega32M1_8h_16690bb6f67e2192a473b405606498a3}




Definition at line 1193 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADIF\_\-REG@{ADIF\_\-REG}}
\index{ADIF\_\-REG@{ADIF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADIF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADIF\_\-REG~ADCSRA}\label{ATmega32M1_8h_4e71a5dff53cb732fdbcf4a21491c1b6}




Definition at line 1194 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADLAR\_\-REG@{ADLAR\_\-REG}}
\index{ADLAR\_\-REG@{ADLAR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADLAR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADLAR\_\-REG~ADMUX}\label{ATmega32M1_8h_18ad16735dc320ce6aa4f9eb80821c40}




Definition at line 261 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADPS0\_\-REG@{ADPS0\_\-REG}}
\index{ADPS0\_\-REG@{ADPS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADPS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADPS0\_\-REG~ADCSRA}\label{ATmega32M1_8h_f68cc59e7b123bb5d4a5127dbaa1a890}




Definition at line 1190 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADPS1\_\-REG@{ADPS1\_\-REG}}
\index{ADPS1\_\-REG@{ADPS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADPS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADPS1\_\-REG~ADCSRA}\label{ATmega32M1_8h_f9c074340db94fcd44c4c7363d850afd}




Definition at line 1191 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADPS2\_\-REG@{ADPS2\_\-REG}}
\index{ADPS2\_\-REG@{ADPS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADPS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADPS2\_\-REG~ADCSRA}\label{ATmega32M1_8h_d1db20ef6588ad97b3639fda5b8dcf42}




Definition at line 1192 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADSC\_\-REG@{ADSC\_\-REG}}
\index{ADSC\_\-REG@{ADSC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADSC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADSC\_\-REG~ADCSRA}\label{ATmega32M1_8h_d53602556f6b1f059170935e12906879}




Definition at line 1196 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADTS0\_\-REG@{ADTS0\_\-REG}}
\index{ADTS0\_\-REG@{ADTS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADTS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADTS0\_\-REG~ADCSRB}\label{ATmega32M1_8h_1ad1344b7dd620d3a791d6faa22f5e17}




Definition at line 1046 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADTS1\_\-REG@{ADTS1\_\-REG}}
\index{ADTS1\_\-REG@{ADTS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADTS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADTS1\_\-REG~ADCSRB}\label{ATmega32M1_8h_e9776ed7eca3fac1b6ab0787632de231}




Definition at line 1047 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADTS2\_\-REG@{ADTS2\_\-REG}}
\index{ADTS2\_\-REG@{ADTS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADTS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADTS2\_\-REG~ADCSRB}\label{ATmega32M1_8h_240983b2c301b45d6efe58b6e36e6b42}




Definition at line 1048 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ADTS3\_\-REG@{ADTS3\_\-REG}}
\index{ADTS3\_\-REG@{ADTS3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ADTS3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ADTS3\_\-REG~ADCSRB}\label{ATmega32M1_8h_e180fdaa8f04b2706d794ca3348a8893}




Definition at line 1049 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AERG\_\-REG@{AERG\_\-REG}}
\index{AERG\_\-REG@{AERG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AERG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AERG\_\-REG~CANGIT}\label{ATmega32M1_8h_666b4dd954380a2558adf47a0f297b80}




Definition at line 587 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AERR\_\-REG@{AERR\_\-REG}}
\index{AERR\_\-REG@{AERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AERR\_\-REG~CANSTMOB}\label{ATmega32M1_8h_c4b9d0aec78070747b4b247cb501721e}




Definition at line 992 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AINC\_\-REG@{AINC\_\-REG}}
\index{AINC\_\-REG@{AINC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AINC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AINC\_\-REG~CANPAGE}\label{ATmega32M1_8h_a58b56679ec7737ae12adf97ca13442d}




Definition at line 361 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0@{AMP0}}
\index{AMP0@{AMP0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0~+\_\-BIT 4}\label{ATmega32M1_8h_d441831e580aa437683755e506f169c0}




Definition at line 1369 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0@{AMP0}}
\index{AMP0@{AMP0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0~+\_\-PORT PORTB}\label{ATmega32M1_8h_d441831e580aa437683755e506f169c0}




Definition at line 1369 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0@{AMP0}}
\index{AMP0@{AMP0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0~-\_\-BIT 3}\label{ATmega32M1_8h_d441831e580aa437683755e506f169c0}




Definition at line 1369 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0@{AMP0}}
\index{AMP0@{AMP0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0~-\_\-PORT PORTB}\label{ATmega32M1_8h_d441831e580aa437683755e506f169c0}




Definition at line 1369 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0EN\_\-REG@{AMP0EN\_\-REG}}
\index{AMP0EN\_\-REG@{AMP0EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0EN\_\-REG~AMP0CSR}\label{ATmega32M1_8h_737064c3638375ab93ad622d83b0b6c7}




Definition at line 1218 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0G0\_\-REG@{AMP0G0\_\-REG}}
\index{AMP0G0\_\-REG@{AMP0G0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0G0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0G0\_\-REG~AMP0CSR}\label{ATmega32M1_8h_30f6b6104d7aebedd83d92e23f5d1140}




Definition at line 1215 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0G1\_\-REG@{AMP0G1\_\-REG}}
\index{AMP0G1\_\-REG@{AMP0G1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0G1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0G1\_\-REG~AMP0CSR}\label{ATmega32M1_8h_7b1e3bc7af337469cf2444c413de647f}




Definition at line 1216 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0IS\_\-REG@{AMP0IS\_\-REG}}
\index{AMP0IS\_\-REG@{AMP0IS\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0IS\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0IS\_\-REG~AMP0CSR}\label{ATmega32M1_8h_5dc32b7092ba5f122ed5b6d659b424c2}




Definition at line 1217 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0ND\_\-REG@{AMP0ND\_\-REG}}
\index{AMP0ND\_\-REG@{AMP0ND\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0ND\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0ND\_\-REG~DIDR1}\label{ATmega32M1_8h_88a7660dc91c1690cc466210195e029c}




Definition at line 413 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0PD\_\-REG@{AMP0PD\_\-REG}}
\index{AMP0PD\_\-REG@{AMP0PD\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0PD\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0PD\_\-REG~DIDR1}\label{ATmega32M1_8h_97e6bc5c1401d3f94f2fc6b621363940}




Definition at line 414 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0TS0\_\-REG@{AMP0TS0\_\-REG}}
\index{AMP0TS0\_\-REG@{AMP0TS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0TS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0TS0\_\-REG~AMP0CSR}\label{ATmega32M1_8h_e6faa80b4cc7f559a5aed1cfcd737cd0}




Definition at line 1211 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0TS1\_\-REG@{AMP0TS1\_\-REG}}
\index{AMP0TS1\_\-REG@{AMP0TS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0TS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0TS1\_\-REG~AMP0CSR}\label{ATmega32M1_8h_374642347db441a29a61a5c4aecca36b}




Definition at line 1212 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP0TS2\_\-REG@{AMP0TS2\_\-REG}}
\index{AMP0TS2\_\-REG@{AMP0TS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP0TS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP0TS2\_\-REG~AMP0CSR}\label{ATmega32M1_8h_46ef2bcc9f8b03f57d62fce83b0bca42}




Definition at line 1213 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1@{AMP1}}
\index{AMP1@{AMP1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1~+\_\-BIT 5}\label{ATmega32M1_8h_38d802f8527d1f9802863e9217d7209d}




Definition at line 1444 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1@{AMP1}}
\index{AMP1@{AMP1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1~+\_\-PORT PORTC}\label{ATmega32M1_8h_38d802f8527d1f9802863e9217d7209d}




Definition at line 1444 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1@{AMP1}}
\index{AMP1@{AMP1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1~-\_\-BIT 4}\label{ATmega32M1_8h_38d802f8527d1f9802863e9217d7209d}




Definition at line 1444 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1@{AMP1}}
\index{AMP1@{AMP1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1~-\_\-PORT PORTC}\label{ATmega32M1_8h_38d802f8527d1f9802863e9217d7209d}




Definition at line 1444 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1EN\_\-REG@{AMP1EN\_\-REG}}
\index{AMP1EN\_\-REG@{AMP1EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1EN\_\-REG~AMP1CSR}\label{ATmega32M1_8h_fab4258b3c202d6c581df4eb149de116}




Definition at line 346 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1G0\_\-REG@{AMP1G0\_\-REG}}
\index{AMP1G0\_\-REG@{AMP1G0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1G0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1G0\_\-REG~AMP1CSR}\label{ATmega32M1_8h_b470e5b542812d224b00906badcb4743}




Definition at line 343 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1G1\_\-REG@{AMP1G1\_\-REG}}
\index{AMP1G1\_\-REG@{AMP1G1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1G1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1G1\_\-REG~AMP1CSR}\label{ATmega32M1_8h_790a29b995c56a308ace85c496f86fc3}




Definition at line 344 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1IS\_\-REG@{AMP1IS\_\-REG}}
\index{AMP1IS\_\-REG@{AMP1IS\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1IS\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1IS\_\-REG~AMP1CSR}\label{ATmega32M1_8h_6f84370b4e0b87cd4fdd7512848670e3}




Definition at line 345 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1TS0\_\-REG@{AMP1TS0\_\-REG}}
\index{AMP1TS0\_\-REG@{AMP1TS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1TS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1TS0\_\-REG~AMP1CSR}\label{ATmega32M1_8h_8df9a78b532eedb0093af3617ad755bc}




Definition at line 339 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1TS1\_\-REG@{AMP1TS1\_\-REG}}
\index{AMP1TS1\_\-REG@{AMP1TS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1TS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1TS1\_\-REG~AMP1CSR}\label{ATmega32M1_8h_992962e48bbda5b865bbe04dbcaebd43}




Definition at line 340 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP1TS2\_\-REG@{AMP1TS2\_\-REG}}
\index{AMP1TS2\_\-REG@{AMP1TS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP1TS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP1TS2\_\-REG~AMP1CSR}\label{ATmega32M1_8h_61c3fdd9fb80ca76317dcfa0c0d8455e}




Definition at line 341 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2@{AMP2}}
\index{AMP2@{AMP2}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2~+\_\-BIT 7}\label{ATmega32M1_8h_b86ffbef7d1a937fd61161dc50fb5d7e}




Definition at line 1460 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2@{AMP2}}
\index{AMP2@{AMP2}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2~+\_\-PORT PORTC}\label{ATmega32M1_8h_b86ffbef7d1a937fd61161dc50fb5d7e}




Definition at line 1460 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2@{AMP2}}
\index{AMP2@{AMP2}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2~-\_\-BIT 5}\label{ATmega32M1_8h_b86ffbef7d1a937fd61161dc50fb5d7e}




Definition at line 1460 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2@{AMP2}}
\index{AMP2@{AMP2}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2~-\_\-PORT PORTB}\label{ATmega32M1_8h_b86ffbef7d1a937fd61161dc50fb5d7e}




Definition at line 1460 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2EN\_\-REG@{AMP2EN\_\-REG}}
\index{AMP2EN\_\-REG@{AMP2EN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2EN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2EN\_\-REG~AMP2CSR}\label{ATmega32M1_8h_b0a772b1d7b4198bfa30c0f404c0387e}




Definition at line 905 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2G0\_\-REG@{AMP2G0\_\-REG}}
\index{AMP2G0\_\-REG@{AMP2G0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2G0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2G0\_\-REG~AMP2CSR}\label{ATmega32M1_8h_594fd2fec7c74d0bdc91faf9ca326c6a}




Definition at line 902 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2G1\_\-REG@{AMP2G1\_\-REG}}
\index{AMP2G1\_\-REG@{AMP2G1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2G1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2G1\_\-REG~AMP2CSR}\label{ATmega32M1_8h_dd6f382f2e840e388255db144b40cae4}




Definition at line 903 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2IS\_\-REG@{AMP2IS\_\-REG}}
\index{AMP2IS\_\-REG@{AMP2IS\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2IS\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2IS\_\-REG~AMP2CSR}\label{ATmega32M1_8h_5c0cceb17b7946a1aa5d3b96b35b0386}




Definition at line 904 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2PD\_\-REG@{AMP2PD\_\-REG}}
\index{AMP2PD\_\-REG@{AMP2PD\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2PD\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2PD\_\-REG~DIDR1}\label{ATmega32M1_8h_dffd6e3d3172033a742e1843acfc034f}




Definition at line 416 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2TS0\_\-REG@{AMP2TS0\_\-REG}}
\index{AMP2TS0\_\-REG@{AMP2TS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2TS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2TS0\_\-REG~AMP2CSR}\label{ATmega32M1_8h_dabd0c63c1b70ae3c7276e7ed1384db2}




Definition at line 898 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2TS1\_\-REG@{AMP2TS1\_\-REG}}
\index{AMP2TS1\_\-REG@{AMP2TS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2TS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2TS1\_\-REG~AMP2CSR}\label{ATmega32M1_8h_7862987d760725911e114edb1e0c6807}




Definition at line 899 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMP2TS2\_\-REG@{AMP2TS2\_\-REG}}
\index{AMP2TS2\_\-REG@{AMP2TS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMP2TS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMP2TS2\_\-REG~AMP2CSR}\label{ATmega32M1_8h_0e718a0dcc64e2dbd4db4caed8f5a771}




Definition at line 900 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMPCMP0\_\-REG@{AMPCMP0\_\-REG}}
\index{AMPCMP0\_\-REG@{AMPCMP0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMPCMP0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMPCMP0\_\-REG~AMP0CSR}\label{ATmega32M1_8h_0f89569aefdcf61d23946fcb2e1b0ad0}




Definition at line 1214 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMPCMP1\_\-REG@{AMPCMP1\_\-REG}}
\index{AMPCMP1\_\-REG@{AMPCMP1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMPCMP1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMPCMP1\_\-REG~AMP1CSR}\label{ATmega32M1_8h_1bc7f74b41c928659c40ad9b06d51cf1}




Definition at line 342 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AMPCMP2\_\-REG@{AMPCMP2\_\-REG}}
\index{AMPCMP2\_\-REG@{AMPCMP2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AMPCMP2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AMPCMP2\_\-REG~AMP2CSR}\label{ATmega32M1_8h_f54936d0ac2a69b71bcc08e9c5087ae8}




Definition at line 901 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!AREFEN\_\-REG@{AREFEN\_\-REG}}
\index{AREFEN\_\-REG@{AREFEN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[AREFEN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define AREFEN\_\-REG~ADCSRB}\label{ATmega32M1_8h_4ab7fa14edb485eb8855929294d870e9}




Definition at line 1050 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BERR\_\-REG@{BERR\_\-REG}}
\index{BERR\_\-REG@{BERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BERR\_\-REG~CANSTMOB}\label{ATmega32M1_8h_e7b6e92fa15234ab20dd9db0485701ec}




Definition at line 996 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BLBSET\_\-REG@{BLBSET\_\-REG}}
\index{BLBSET\_\-REG@{BLBSET\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BLBSET\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BLBSET\_\-REG~SPMCSR}\label{ATmega32M1_8h_7c8a500e5b966a8af0033b0bd9b3dd23}




Definition at line 1133 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BOFF\_\-REG@{BOFF\_\-REG}}
\index{BOFF\_\-REG@{BOFF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BOFF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BOFF\_\-REG~CANGSTA}\label{ATmega32M1_8h_343f14dbddc547f68c00e558d35b6a99}




Definition at line 287 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BOFFIT\_\-REG@{BOFFIT\_\-REG}}
\index{BOFFIT\_\-REG@{BOFFIT\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BOFFIT\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BOFFIT\_\-REG~CANGIT}\label{ATmega32M1_8h_30419455348240bddd8a12de7793ba58}




Definition at line 593 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BORF\_\-REG@{BORF\_\-REG}}
\index{BORF\_\-REG@{BORF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BORF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BORF\_\-REG~MCUSR}\label{ATmega32M1_8h_286e3a35e3f66ada8021a22cc44b268d}




Definition at line 853 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BRP0\_\-REG@{BRP0\_\-REG}}
\index{BRP0\_\-REG@{BRP0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BRP0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BRP0\_\-REG~CANBT1}\label{ATmega32M1_8h_db4bfd706b83758911dc6f528787e183}




Definition at line 1172 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BRP1\_\-REG@{BRP1\_\-REG}}
\index{BRP1\_\-REG@{BRP1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BRP1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BRP1\_\-REG~CANBT1}\label{ATmega32M1_8h_3dc8933deb2b38ecead5f6afefe5bfa9}




Definition at line 1173 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BRP2\_\-REG@{BRP2\_\-REG}}
\index{BRP2\_\-REG@{BRP2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BRP2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BRP2\_\-REG~CANBT1}\label{ATmega32M1_8h_9e0c29f434b4b72168b2f9515775a9e9}




Definition at line 1174 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BRP3\_\-REG@{BRP3\_\-REG}}
\index{BRP3\_\-REG@{BRP3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BRP3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BRP3\_\-REG~CANBT1}\label{ATmega32M1_8h_6c5e8ee4c3b08ceedeaf21bf6a2b740c}




Definition at line 1175 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BRP4\_\-REG@{BRP4\_\-REG}}
\index{BRP4\_\-REG@{BRP4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BRP4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BRP4\_\-REG~CANBT1}\label{ATmega32M1_8h_23885ff2e22c25ee7a1275684d8e79f9}




Definition at line 1176 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BRP5\_\-REG@{BRP5\_\-REG}}
\index{BRP5\_\-REG@{BRP5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BRP5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BRP5\_\-REG~CANBT1}\label{ATmega32M1_8h_8ec9ac742425038894613346c61bf27e}




Definition at line 1177 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!BXOK\_\-REG@{BXOK\_\-REG}}
\index{BXOK\_\-REG@{BXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[BXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define BXOK\_\-REG~CANGIT}\label{ATmega32M1_8h_c0fd9404cb4f87c060282c8aba15f79b}




Definition at line 591 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!C\_\-REG@{C\_\-REG}}
\index{C\_\-REG@{C\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[C\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define C\_\-REG~SREG}\label{ATmega32M1_8h_5335949b52f31553bda075c17e0de4d8}




Definition at line 908 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL0\_\-REG@{CAL0\_\-REG}}
\index{CAL0\_\-REG@{CAL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL0\_\-REG~OSCCAL}\label{ATmega32M1_8h_df55f8f719da36797791c181e4f66f6b}




Definition at line 531 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL1\_\-REG@{CAL1\_\-REG}}
\index{CAL1\_\-REG@{CAL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL1\_\-REG~OSCCAL}\label{ATmega32M1_8h_0a9ed4d8419b97d6ff0e5cd7bff4581b}




Definition at line 532 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL2\_\-REG@{CAL2\_\-REG}}
\index{CAL2\_\-REG@{CAL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL2\_\-REG~OSCCAL}\label{ATmega32M1_8h_b3cf18efc048d1ecd21daaf89179e4b1}




Definition at line 533 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL3\_\-REG@{CAL3\_\-REG}}
\index{CAL3\_\-REG@{CAL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL3\_\-REG~OSCCAL}\label{ATmega32M1_8h_03ae39f286bd0de01594965a9158d199}




Definition at line 534 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL4\_\-REG@{CAL4\_\-REG}}
\index{CAL4\_\-REG@{CAL4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL4\_\-REG~OSCCAL}\label{ATmega32M1_8h_fdce051f636e620501c18b27bcea8cfc}




Definition at line 535 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL5\_\-REG@{CAL5\_\-REG}}
\index{CAL5\_\-REG@{CAL5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL5\_\-REG~OSCCAL}\label{ATmega32M1_8h_a26dd5b51d581de16cb1fae22340aabc}




Definition at line 536 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CAL6\_\-REG@{CAL6\_\-REG}}
\index{CAL6\_\-REG@{CAL6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CAL6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CAL6\_\-REG~OSCCAL}\label{ATmega32M1_8h_92798a38b8c56009490e5f8f3d716b7b}




Definition at line 537 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CANIT\_\-REG@{CANIT\_\-REG}}
\index{CANIT\_\-REG@{CANIT\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CANIT\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CANIT\_\-REG~CANGIT}\label{ATmega32M1_8h_d36fc26a9c3a05f2b871a1bc52f115a6}




Definition at line 594 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CERG\_\-REG@{CERG\_\-REG}}
\index{CERG\_\-REG@{CERG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CERG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CERG\_\-REG~CANGIT}\label{ATmega32M1_8h_3d8b7aa25717bff65c338995ef2d0817}




Definition at line 589 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CERR\_\-REG@{CERR\_\-REG}}
\index{CERR\_\-REG@{CERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CERR\_\-REG~CANSTMOB}\label{ATmega32M1_8h_421043de2f98f3a45acfb74726d6d9b5}




Definition at line 994 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CGP0\_\-REG@{CGP0\_\-REG}}
\index{CGP0\_\-REG@{CGP0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CGP0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CGP0\_\-REG~CANHPMOB}\label{ATmega32M1_8h_5af8719e93a09d1fc58c6533e038edda}




Definition at line 811 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CGP1\_\-REG@{CGP1\_\-REG}}
\index{CGP1\_\-REG@{CGP1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CGP1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CGP1\_\-REG~CANHPMOB}\label{ATmega32M1_8h_da25bc11f2807336cc76c26582ebcae3}




Definition at line 812 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CGP2\_\-REG@{CGP2\_\-REG}}
\index{CGP2\_\-REG@{CGP2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CGP2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CGP2\_\-REG~CANHPMOB}\label{ATmega32M1_8h_1619b2db268d1d23f2a0df403ea85048}




Definition at line 813 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CGP3\_\-REG@{CGP3\_\-REG}}
\index{CGP3\_\-REG@{CGP3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CGP3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CGP3\_\-REG~CANHPMOB}\label{ATmega32M1_8h_2f0974e867664eff754a3ccce1feca45}




Definition at line 814 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLK0\_\-BIT@{CLK0\_\-BIT}}
\index{CLK0\_\-BIT@{CLK0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLK0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define CLK0\_\-BIT~1}\label{ATmega32M1_8h_e9ed2dd012906e7a4a39a09839d6996f}




Definition at line 1472 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLK0\_\-PORT@{CLK0\_\-PORT}}
\index{CLK0\_\-PORT@{CLK0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLK0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define CLK0\_\-PORT~PORTD}\label{ATmega32M1_8h_748ff96f52971fde47cfe7765e8a6d9a}




Definition at line 1471 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLKPCE\_\-REG@{CLKPCE\_\-REG}}
\index{CLKPCE\_\-REG@{CLKPCE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLKPCE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CLKPCE\_\-REG~CLKPR}\label{ATmega32M1_8h_f47b15cca377c713bbb974d80f62bf61}




Definition at line 429 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLKPS0\_\-REG@{CLKPS0\_\-REG}}
\index{CLKPS0\_\-REG@{CLKPS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLKPS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CLKPS0\_\-REG~CLKPR}\label{ATmega32M1_8h_a2553ac5adab16a1adef82b97aa410ff}




Definition at line 425 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLKPS1\_\-REG@{CLKPS1\_\-REG}}
\index{CLKPS1\_\-REG@{CLKPS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLKPS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CLKPS1\_\-REG~CLKPR}\label{ATmega32M1_8h_f7ff7982bf20c50da2500d70b568a2b2}




Definition at line 426 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLKPS2\_\-REG@{CLKPS2\_\-REG}}
\index{CLKPS2\_\-REG@{CLKPS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLKPS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CLKPS2\_\-REG~CLKPR}\label{ATmega32M1_8h_4b49b376cac97e02f93fdca8d8706da4}




Definition at line 427 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CLKPS3\_\-REG@{CLKPS3\_\-REG}}
\index{CLKPS3\_\-REG@{CLKPS3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CLKPS3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CLKPS3\_\-REG~CLKPR}\label{ATmega32M1_8h_3dc9e95a762e3b195323bcbaa4fd450d}




Definition at line 428 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM0A0\_\-REG@{COM0A0\_\-REG}}
\index{COM0A0\_\-REG@{COM0A0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM0A0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM0A0\_\-REG~TCCR0A}\label{ATmega32M1_8h_9c9465ff0fee821ed1763c20125f47a3}




Definition at line 686 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM0A1\_\-REG@{COM0A1\_\-REG}}
\index{COM0A1\_\-REG@{COM0A1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM0A1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM0A1\_\-REG~TCCR0A}\label{ATmega32M1_8h_3def34db20518881afd8dd086ffb398c}




Definition at line 687 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM0B0\_\-REG@{COM0B0\_\-REG}}
\index{COM0B0\_\-REG@{COM0B0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM0B0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM0B0\_\-REG~TCCR0A}\label{ATmega32M1_8h_9d23e2b8a3ebfce4226155d1ee5862a9}




Definition at line 684 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM0B1\_\-REG@{COM0B1\_\-REG}}
\index{COM0B1\_\-REG@{COM0B1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM0B1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM0B1\_\-REG~TCCR0A}\label{ATmega32M1_8h_2ce4faf67e1d6fe840938a8c4945b0eb}




Definition at line 685 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM1A0\_\-REG@{COM1A0\_\-REG}}
\index{COM1A0\_\-REG@{COM1A0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM1A0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM1A0\_\-REG~TCCR1A}\label{ATmega32M1_8h_d37d490b8d5e4d80917f0983234f2c5a}




Definition at line 1059 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM1A1\_\-REG@{COM1A1\_\-REG}}
\index{COM1A1\_\-REG@{COM1A1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM1A1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM1A1\_\-REG~TCCR1A}\label{ATmega32M1_8h_57ab2253fc5ec61d0288edeaa1fd8ce0}




Definition at line 1060 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM1B0\_\-REG@{COM1B0\_\-REG}}
\index{COM1B0\_\-REG@{COM1B0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM1B0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM1B0\_\-REG~TCCR1A}\label{ATmega32M1_8h_5690d6e81fd612acd36b83e7af505143}




Definition at line 1057 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!COM1B1\_\-REG@{COM1B1\_\-REG}}
\index{COM1B1\_\-REG@{COM1B1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[COM1B1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define COM1B1\_\-REG~TCCR1A}\label{ATmega32M1_8h_be50faa4969da6cc0e2e7f0f16cfd19c}




Definition at line 1058 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CONMOB0\_\-REG@{CONMOB0\_\-REG}}
\index{CONMOB0\_\-REG@{CONMOB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CONMOB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CONMOB0\_\-REG~CANCDMOB}\label{ATmega32M1_8h_dc81ea3c10c4bcbdf4c3c314faaed1bf}




Definition at line 797 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CONMOB1\_\-REG@{CONMOB1\_\-REG}}
\index{CONMOB1\_\-REG@{CONMOB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CONMOB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CONMOB1\_\-REG~CANCDMOB}\label{ATmega32M1_8h_d88355e91a4ff084d8bf70d0a3b9df8b}




Definition at line 798 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CPHA\_\-REG@{CPHA\_\-REG}}
\index{CPHA\_\-REG@{CPHA\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CPHA\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CPHA\_\-REG~SPCR}\label{ATmega32M1_8h_a28c55e26ba79805e7da354a966d5451}




Definition at line 713 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CPOL\_\-REG@{CPOL\_\-REG}}
\index{CPOL\_\-REG@{CPOL\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CPOL\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CPOL\_\-REG~SPCR}\label{ATmega32M1_8h_7eb3eef757d7506a6dafa0b370a10b63}




Definition at line 714 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CS00\_\-REG@{CS00\_\-REG}}
\index{CS00\_\-REG@{CS00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CS00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CS00\_\-REG~TCCR0B}\label{ATmega32M1_8h_d6fb22c4ce97d412dc37b55f4b35ee93}




Definition at line 668 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CS01\_\-REG@{CS01\_\-REG}}
\index{CS01\_\-REG@{CS01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CS01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CS01\_\-REG~TCCR0B}\label{ATmega32M1_8h_d7a4fa68797c75de6a1926be1cfec45c}




Definition at line 669 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CS02\_\-REG@{CS02\_\-REG}}
\index{CS02\_\-REG@{CS02\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CS02\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CS02\_\-REG~TCCR0B}\label{ATmega32M1_8h_1a9315fba28730441e7c82bb275bb9c3}




Definition at line 670 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CS10\_\-REG@{CS10\_\-REG}}
\index{CS10\_\-REG@{CS10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CS10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CS10\_\-REG~TCCR1B}\label{ATmega32M1_8h_4bccf13bfda930e64185bba13885c648}




Definition at line 1113 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CS11\_\-REG@{CS11\_\-REG}}
\index{CS11\_\-REG@{CS11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CS11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CS11\_\-REG~TCCR1B}\label{ATmega32M1_8h_d99924dd14efce240828bab9be7449fe}




Definition at line 1114 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!CS12\_\-REG@{CS12\_\-REG}}
\index{CS12\_\-REG@{CS12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[CS12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define CS12\_\-REG~TCCR1B}\label{ATmega32M1_8h_e76fac75534b9165e7c6b5df064b14b5}




Definition at line 1115 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!D2A\_\-BIT@{D2A\_\-BIT}}
\index{D2A\_\-BIT@{D2A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[D2A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define D2A\_\-BIT~7}\label{ATmega32M1_8h_d62a0cb5c45c4cad6155d29cd3daf18b}




Definition at line 1458 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!D2A\_\-PORT@{D2A\_\-PORT}}
\index{D2A\_\-PORT@{D2A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[D2A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define D2A\_\-PORT~PORTC}\label{ATmega32M1_8h_6bb5e0a856b2fdadf3d8332f4262cdc2}




Definition at line 1457 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DAATE\_\-REG@{DAATE\_\-REG}}
\index{DAATE\_\-REG@{DAATE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DAATE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DAATE\_\-REG~DACON}\label{ATmega32M1_8h_302d56ff28092da4796e5939419fd80e}




Definition at line 1226 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH0\_\-REG@{DACH0\_\-REG}}
\index{DACH0\_\-REG@{DACH0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH0\_\-REG~DACH}\label{ATmega32M1_8h_147de2771e7336af523e90b1952cfb01}




Definition at line 1018 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH1\_\-REG@{DACH1\_\-REG}}
\index{DACH1\_\-REG@{DACH1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH1\_\-REG~DACH}\label{ATmega32M1_8h_4c3c79bd12853c2cb8fb397ad0b60b62}




Definition at line 1019 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH2\_\-REG@{DACH2\_\-REG}}
\index{DACH2\_\-REG@{DACH2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH2\_\-REG~DACH}\label{ATmega32M1_8h_c0939907b0634c7e93d4d66a830c0c49}




Definition at line 1020 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH3\_\-REG@{DACH3\_\-REG}}
\index{DACH3\_\-REG@{DACH3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH3\_\-REG~DACH}\label{ATmega32M1_8h_4ed50b236660f1b2b5b0fe8331ca55e8}




Definition at line 1021 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH4\_\-REG@{DACH4\_\-REG}}
\index{DACH4\_\-REG@{DACH4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH4\_\-REG~DACH}\label{ATmega32M1_8h_e666d91b2ee21641b5a4673902dd629c}




Definition at line 1022 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH5\_\-REG@{DACH5\_\-REG}}
\index{DACH5\_\-REG@{DACH5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH5\_\-REG~DACH}\label{ATmega32M1_8h_827fd15ef44df078a35df6a82bcca0d1}




Definition at line 1023 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH6\_\-REG@{DACH6\_\-REG}}
\index{DACH6\_\-REG@{DACH6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH6\_\-REG~DACH}\label{ATmega32M1_8h_d20a31fe6902fd00048e3a11314fab81}




Definition at line 1024 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACH7\_\-REG@{DACH7\_\-REG}}
\index{DACH7\_\-REG@{DACH7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACH7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACH7\_\-REG~DACH}\label{ATmega32M1_8h_8f2f3ec0cd16d80b77badc9825e71158}




Definition at line 1025 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL0\_\-REG@{DACL0\_\-REG}}
\index{DACL0\_\-REG@{DACL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL0\_\-REG~DACL}\label{ATmega32M1_8h_41837a6572e215ccd15e7e180757ea5b}




Definition at line 1028 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL1\_\-REG@{DACL1\_\-REG}}
\index{DACL1\_\-REG@{DACL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL1\_\-REG~DACL}\label{ATmega32M1_8h_121e7de5c268637c6d9b00203cccdc9f}




Definition at line 1029 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL2\_\-REG@{DACL2\_\-REG}}
\index{DACL2\_\-REG@{DACL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL2\_\-REG~DACL}\label{ATmega32M1_8h_f9ea459127eb70a78b8217ba9728b214}




Definition at line 1030 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL3\_\-REG@{DACL3\_\-REG}}
\index{DACL3\_\-REG@{DACL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL3\_\-REG~DACL}\label{ATmega32M1_8h_f89781b77a8510d1ec54e2db02bcf18a}




Definition at line 1031 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL4\_\-REG@{DACL4\_\-REG}}
\index{DACL4\_\-REG@{DACL4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL4\_\-REG~DACL}\label{ATmega32M1_8h_c770e6b7faaf0518d21a4fe7de646c9b}




Definition at line 1032 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL5\_\-REG@{DACL5\_\-REG}}
\index{DACL5\_\-REG@{DACL5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL5\_\-REG~DACL}\label{ATmega32M1_8h_05946184584b37d9a0b109379f490231}




Definition at line 1033 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL6\_\-REG@{DACL6\_\-REG}}
\index{DACL6\_\-REG@{DACL6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL6\_\-REG~DACL}\label{ATmega32M1_8h_b6ce90d897a2c9449db02df615ac501d}




Definition at line 1034 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DACL7\_\-REG@{DACL7\_\-REG}}
\index{DACL7\_\-REG@{DACL7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DACL7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DACL7\_\-REG~DACL}\label{ATmega32M1_8h_07d31768bbded2e2bbec5a4a152b62be}




Definition at line 1035 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DAEN\_\-REG@{DAEN\_\-REG}}
\index{DAEN\_\-REG@{DAEN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DAEN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DAEN\_\-REG~DACON}\label{ATmega32M1_8h_93e1f50f1bd4090ae2da49104ce29936}




Definition at line 1221 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DALA\_\-REG@{DALA\_\-REG}}
\index{DALA\_\-REG@{DALA\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DALA\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DALA\_\-REG~DACON}\label{ATmega32M1_8h_247f601fb72332a3c5b7b16966dc9443}




Definition at line 1222 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DATS0\_\-REG@{DATS0\_\-REG}}
\index{DATS0\_\-REG@{DATS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DATS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DATS0\_\-REG~DACON}\label{ATmega32M1_8h_1879d55cc244ca8775deb90a270981c5}




Definition at line 1223 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DATS1\_\-REG@{DATS1\_\-REG}}
\index{DATS1\_\-REG@{DATS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DATS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DATS1\_\-REG~DACON}\label{ATmega32M1_8h_0102b6469b242512b75aa364faa0f649}




Definition at line 1224 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DATS2\_\-REG@{DATS2\_\-REG}}
\index{DATS2\_\-REG@{DATS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DATS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DATS2\_\-REG~DACON}\label{ATmega32M1_8h_7c1dedc9337b93e5caaddd3a9c723302}




Definition at line 1225 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB0\_\-REG@{DDB0\_\-REG}}
\index{DDB0\_\-REG@{DDB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB0\_\-REG~DDRB}\label{ATmega32M1_8h_7ab353495cd33f8c72f46e7d319c703a}




Definition at line 487 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB1\_\-REG@{DDB1\_\-REG}}
\index{DDB1\_\-REG@{DDB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB1\_\-REG~DDRB}\label{ATmega32M1_8h_39058410287a0eeec43e291e018d01c1}




Definition at line 488 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB2\_\-REG@{DDB2\_\-REG}}
\index{DDB2\_\-REG@{DDB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB2\_\-REG~DDRB}\label{ATmega32M1_8h_29d74f0664c454064897591d1919b293}




Definition at line 489 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB3\_\-REG@{DDB3\_\-REG}}
\index{DDB3\_\-REG@{DDB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB3\_\-REG~DDRB}\label{ATmega32M1_8h_d8a09112abdf6f164c8a71f18e8c612a}




Definition at line 490 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB4\_\-REG@{DDB4\_\-REG}}
\index{DDB4\_\-REG@{DDB4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB4\_\-REG~DDRB}\label{ATmega32M1_8h_a15b3fe8b6fe58f7212e9c5d34aef6fb}




Definition at line 491 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB5\_\-REG@{DDB5\_\-REG}}
\index{DDB5\_\-REG@{DDB5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB5\_\-REG~DDRB}\label{ATmega32M1_8h_d67c06d800fb1f86170187f1a5aca74c}




Definition at line 492 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB6\_\-REG@{DDB6\_\-REG}}
\index{DDB6\_\-REG@{DDB6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB6\_\-REG~DDRB}\label{ATmega32M1_8h_319ef0c4c664b7b3242a2d4a39ecf8c8}




Definition at line 493 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDB7\_\-REG@{DDB7\_\-REG}}
\index{DDB7\_\-REG@{DDB7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDB7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDB7\_\-REG~DDRB}\label{ATmega32M1_8h_e4947913fc9208758819398510f06aee}




Definition at line 494 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC0\_\-REG@{DDC0\_\-REG}}
\index{DDC0\_\-REG@{DDC0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC0\_\-REG~DDRC}\label{ATmega32M1_8h_ccb031d620f90f87b9e327870bdf59dd}




Definition at line 497 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC1\_\-REG@{DDC1\_\-REG}}
\index{DDC1\_\-REG@{DDC1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC1\_\-REG~DDRC}\label{ATmega32M1_8h_5ab261a81b4dfb408e820cacc0514dc1}




Definition at line 498 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC2\_\-REG@{DDC2\_\-REG}}
\index{DDC2\_\-REG@{DDC2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC2\_\-REG~DDRC}\label{ATmega32M1_8h_14f193e23e47dc3b05a0c3c788f99094}




Definition at line 499 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC3\_\-REG@{DDC3\_\-REG}}
\index{DDC3\_\-REG@{DDC3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC3\_\-REG~DDRC}\label{ATmega32M1_8h_853326d165a156927b784397e90ad894}




Definition at line 500 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC4\_\-REG@{DDC4\_\-REG}}
\index{DDC4\_\-REG@{DDC4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC4\_\-REG~DDRC}\label{ATmega32M1_8h_c0dff827fa20acaa7dfd65d12d051790}




Definition at line 501 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC5\_\-REG@{DDC5\_\-REG}}
\index{DDC5\_\-REG@{DDC5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC5\_\-REG~DDRC}\label{ATmega32M1_8h_cb4f346aaa12df48a35785cc91c860ec}




Definition at line 502 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC6\_\-REG@{DDC6\_\-REG}}
\index{DDC6\_\-REG@{DDC6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC6\_\-REG~DDRC}\label{ATmega32M1_8h_fa585648fdb2e0cd7f82356ffd85f800}




Definition at line 503 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDC7\_\-REG@{DDC7\_\-REG}}
\index{DDC7\_\-REG@{DDC7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDC7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDC7\_\-REG~DDRC}\label{ATmega32M1_8h_a7a12a92a1b07528bf30f7fa8e367fd1}




Definition at line 504 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD0\_\-REG@{DDD0\_\-REG}}
\index{DDD0\_\-REG@{DDD0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD0\_\-REG~DDRD}\label{ATmega32M1_8h_152c8fee78340e396d3024e7cea88433}




Definition at line 540 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD1\_\-REG@{DDD1\_\-REG}}
\index{DDD1\_\-REG@{DDD1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD1\_\-REG~DDRD}\label{ATmega32M1_8h_be7032a0e18a85f4cd6d060a64802566}




Definition at line 541 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD2\_\-REG@{DDD2\_\-REG}}
\index{DDD2\_\-REG@{DDD2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD2\_\-REG~DDRD}\label{ATmega32M1_8h_bbe07d30279007bfe09792104c6dfae7}




Definition at line 542 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD3\_\-REG@{DDD3\_\-REG}}
\index{DDD3\_\-REG@{DDD3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD3\_\-REG~DDRD}\label{ATmega32M1_8h_b7ef0460abb65fc1170e8d2c314c12ff}




Definition at line 543 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD4\_\-REG@{DDD4\_\-REG}}
\index{DDD4\_\-REG@{DDD4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD4\_\-REG~DDRD}\label{ATmega32M1_8h_e3593bcbd12aa648e0a7021f766af483}




Definition at line 544 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD5\_\-REG@{DDD5\_\-REG}}
\index{DDD5\_\-REG@{DDD5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD5\_\-REG~DDRD}\label{ATmega32M1_8h_67f8dedc7647fb0bf35e667b352b6dd3}




Definition at line 545 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD6\_\-REG@{DDD6\_\-REG}}
\index{DDD6\_\-REG@{DDD6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD6\_\-REG~DDRD}\label{ATmega32M1_8h_04fec946d7891b6088ae9f626507a3a0}




Definition at line 546 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDD7\_\-REG@{DDD7\_\-REG}}
\index{DDD7\_\-REG@{DDD7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDD7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDD7\_\-REG~DDRD}\label{ATmega32M1_8h_ba6ff69f61f7b43237f9fff3c21bcc44}




Definition at line 547 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDE0\_\-REG@{DDE0\_\-REG}}
\index{DDE0\_\-REG@{DDE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDE0\_\-REG~DDRE}\label{ATmega32M1_8h_f6c4c974cabea11e29b793c19cd08ee7}




Definition at line 706 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDE1\_\-REG@{DDE1\_\-REG}}
\index{DDE1\_\-REG@{DDE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDE1\_\-REG~DDRE}\label{ATmega32M1_8h_951ce14677baf7e5d707c6f6a937960e}




Definition at line 707 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DDE2\_\-REG@{DDE2\_\-REG}}
\index{DDE2\_\-REG@{DDE2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DDE2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DDE2\_\-REG~DDRE}\label{ATmega32M1_8h_558153db32399a2160a68bda8ffb20c0}




Definition at line 708 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DLC0\_\-REG@{DLC0\_\-REG}}
\index{DLC0\_\-REG@{DLC0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DLC0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DLC0\_\-REG~CANCDMOB}\label{ATmega32M1_8h_a6af0b3a985415f6cb0acf66e4a20faa}




Definition at line 791 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DLC1\_\-REG@{DLC1\_\-REG}}
\index{DLC1\_\-REG@{DLC1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DLC1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DLC1\_\-REG~CANCDMOB}\label{ATmega32M1_8h_f048617f16cfe9a50a761b246a445843}




Definition at line 792 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DLC2\_\-REG@{DLC2\_\-REG}}
\index{DLC2\_\-REG@{DLC2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DLC2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DLC2\_\-REG~CANCDMOB}\label{ATmega32M1_8h_cbc55b19a8c6bf4a293b557ef1d6a78c}




Definition at line 793 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DLC3\_\-REG@{DLC3\_\-REG}}
\index{DLC3\_\-REG@{DLC3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DLC3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DLC3\_\-REG~CANCDMOB}\label{ATmega32M1_8h_492e1d3aa07b5a1b9480db3eb94317a7}




Definition at line 794 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DLCW\_\-REG@{DLCW\_\-REG}}
\index{DLCW\_\-REG@{DLCW\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DLCW\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DLCW\_\-REG~CANSTMOB}\label{ATmega32M1_8h_e66c3e0ee3be1f7182c6ea5fb293fc85}




Definition at line 999 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!DORD\_\-REG@{DORD\_\-REG}}
\index{DORD\_\-REG@{DORD\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[DORD\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define DORD\_\-REG~SPCR}\label{ATmega32M1_8h_784483b3c181bd9477265a1a9d9d457d}




Definition at line 716 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR0\_\-REG@{EEAR0\_\-REG}}
\index{EEAR0\_\-REG@{EEAR0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR0\_\-REG~EEARL}\label{ATmega32M1_8h_e1187c7c4a9a2c9a94c52f960aea72b7}




Definition at line 976 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR1\_\-REG@{EEAR1\_\-REG}}
\index{EEAR1\_\-REG@{EEAR1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR1\_\-REG~EEARL}\label{ATmega32M1_8h_3ecedc062008b7de245537691bab01a0}




Definition at line 977 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR2\_\-REG@{EEAR2\_\-REG}}
\index{EEAR2\_\-REG@{EEAR2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR2\_\-REG~EEARL}\label{ATmega32M1_8h_d20f65b0b26eb04cfd85d58a61f1144c}




Definition at line 978 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR3\_\-REG@{EEAR3\_\-REG}}
\index{EEAR3\_\-REG@{EEAR3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR3\_\-REG~EEARL}\label{ATmega32M1_8h_c62f3e15dcda82565987d6f2c5d085b7}




Definition at line 979 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR4\_\-REG@{EEAR4\_\-REG}}
\index{EEAR4\_\-REG@{EEAR4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR4\_\-REG~EEARL}\label{ATmega32M1_8h_f5c808944940e03de96e4bc7b24c193e}




Definition at line 980 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR5\_\-REG@{EEAR5\_\-REG}}
\index{EEAR5\_\-REG@{EEAR5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR5\_\-REG~EEARL}\label{ATmega32M1_8h_89176301c1e1a7567b527dd3125e644b}




Definition at line 981 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR6\_\-REG@{EEAR6\_\-REG}}
\index{EEAR6\_\-REG@{EEAR6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR6\_\-REG~EEARL}\label{ATmega32M1_8h_8ef30328fa9ddb4fffdf336ef09c9e47}




Definition at line 982 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR7\_\-REG@{EEAR7\_\-REG}}
\index{EEAR7\_\-REG@{EEAR7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR7\_\-REG~EEARL}\label{ATmega32M1_8h_c21ffe3cf613f29c03684fd7b88e0678}




Definition at line 983 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR8\_\-REG@{EEAR8\_\-REG}}
\index{EEAR8\_\-REG@{EEAR8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR8\_\-REG~EEARH}\label{ATmega32M1_8h_f220aa494c268a9bccf6bd06bbdbd8b5}




Definition at line 276 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEAR9\_\-REG@{EEAR9\_\-REG}}
\index{EEAR9\_\-REG@{EEAR9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEAR9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEAR9\_\-REG~EEARH}\label{ATmega32M1_8h_e2337b0f23a8490018c6d10afa88120b}




Definition at line 277 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR0\_\-REG@{EEDR0\_\-REG}}
\index{EEDR0\_\-REG@{EEDR0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR0\_\-REG~EEDR}\label{ATmega32M1_8h_8d216943a0cca47e19d07df2e094dd0c}




Definition at line 154 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR1\_\-REG@{EEDR1\_\-REG}}
\index{EEDR1\_\-REG@{EEDR1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR1\_\-REG~EEDR}\label{ATmega32M1_8h_91207268cff90964d03fba66dcf40c9b}




Definition at line 155 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR2\_\-REG@{EEDR2\_\-REG}}
\index{EEDR2\_\-REG@{EEDR2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR2\_\-REG~EEDR}\label{ATmega32M1_8h_381678d278d3388ee7402642d9356e89}




Definition at line 156 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR3\_\-REG@{EEDR3\_\-REG}}
\index{EEDR3\_\-REG@{EEDR3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR3\_\-REG~EEDR}\label{ATmega32M1_8h_10c53e9f8101929b0c98c7b648adf7b2}




Definition at line 157 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR4\_\-REG@{EEDR4\_\-REG}}
\index{EEDR4\_\-REG@{EEDR4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR4\_\-REG~EEDR}\label{ATmega32M1_8h_ec27ae2a8bbeab97b48f69d029778688}




Definition at line 158 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR5\_\-REG@{EEDR5\_\-REG}}
\index{EEDR5\_\-REG@{EEDR5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR5\_\-REG~EEDR}\label{ATmega32M1_8h_4e36ce79337901ade900f6b39e0b5cbd}




Definition at line 159 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR6\_\-REG@{EEDR6\_\-REG}}
\index{EEDR6\_\-REG@{EEDR6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR6\_\-REG~EEDR}\label{ATmega32M1_8h_7507ac912d4263b41db72ec4ea316e3d}




Definition at line 160 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEDR7\_\-REG@{EEDR7\_\-REG}}
\index{EEDR7\_\-REG@{EEDR7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEDR7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEDR7\_\-REG~EEDR}\label{ATmega32M1_8h_1f0ea61a10f28c018a87bd8c80b1d1d0}




Definition at line 161 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEMWE\_\-REG@{EEMWE\_\-REG}}
\index{EEMWE\_\-REG@{EEMWE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEMWE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEMWE\_\-REG~EECR}\label{ATmega32M1_8h_648db690fddba5eba089ab8ea3aa6165}




Definition at line 859 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEPM0\_\-REG@{EEPM0\_\-REG}}
\index{EEPM0\_\-REG@{EEPM0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEPM0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEPM0\_\-REG~EECR}\label{ATmega32M1_8h_39008c85a0c5358e43b2b21db76547c5}




Definition at line 861 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEPM1\_\-REG@{EEPM1\_\-REG}}
\index{EEPM1\_\-REG@{EEPM1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEPM1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEPM1\_\-REG~EECR}\label{ATmega32M1_8h_af8ab5d087a0eb2543074269e8a55611}




Definition at line 862 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EERE\_\-REG@{EERE\_\-REG}}
\index{EERE\_\-REG@{EERE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EERE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EERE\_\-REG~EECR}\label{ATmega32M1_8h_4b0a037ffc07086c66641e936e4ab391}




Definition at line 857 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EERIE\_\-REG@{EERIE\_\-REG}}
\index{EERIE\_\-REG@{EERIE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EERIE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EERIE\_\-REG~EECR}\label{ATmega32M1_8h_4807b87f52b0b2e793969557480bdb25}




Definition at line 860 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EEWE\_\-REG@{EEWE\_\-REG}}
\index{EEWE\_\-REG@{EEWE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EEWE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EEWE\_\-REG~EECR}\label{ATmega32M1_8h_6d685ff735652a80d17978810c487410}




Definition at line 858 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENASTB\_\-REG@{ENASTB\_\-REG}}
\index{ENASTB\_\-REG@{ENASTB\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENASTB\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENASTB\_\-REG~CANGCON}\label{ATmega32M1_8h_abf39ebb705f676ca79a2015043d11aa}




Definition at line 295 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENBOFF\_\-REG@{ENBOFF\_\-REG}}
\index{ENBOFF\_\-REG@{ENBOFF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENBOFF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENBOFF\_\-REG~CANGIE}\label{ATmega32M1_8h_42bfad92a9317a976ebc4cd2661ceee1}




Definition at line 628 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENBX\_\-REG@{ENBX\_\-REG}}
\index{ENBX\_\-REG@{ENBX\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENBX\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENBX\_\-REG~CANGIE}\label{ATmega32M1_8h_08a9561dbf47317fa3cf2d75e0711b63}




Definition at line 624 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENERG\_\-REG@{ENERG\_\-REG}}
\index{ENERG\_\-REG@{ENERG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENERG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENERG\_\-REG~CANGIE}\label{ATmega32M1_8h_58f69c23118a5d053e1bb60b42e4c8a8}




Definition at line 623 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENERR\_\-REG@{ENERR\_\-REG}}
\index{ENERR\_\-REG@{ENERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENERR\_\-REG~CANGIE}\label{ATmega32M1_8h_e8dba34a92aeed48e30d39b91de074f4}




Definition at line 625 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENFG\_\-REG@{ENFG\_\-REG}}
\index{ENFG\_\-REG@{ENFG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENFG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENFG\_\-REG~CANGSTA}\label{ATmega32M1_8h_c87a742a0e8311b705e6e27fee6b8c6a}




Definition at line 288 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENIT\_\-REG@{ENIT\_\-REG}}
\index{ENIT\_\-REG@{ENIT\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENIT\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENIT\_\-REG~CANGIE}\label{ATmega32M1_8h_c08216b989dd926f8c3ce60b06eb0420}




Definition at line 629 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENMOB0\_\-REG@{ENMOB0\_\-REG}}
\index{ENMOB0\_\-REG@{ENMOB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENMOB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENMOB0\_\-REG~CANEN2}\label{ATmega32M1_8h_b30ef2156e9b547638ca93b0bc89f107}




Definition at line 1038 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENMOB1\_\-REG@{ENMOB1\_\-REG}}
\index{ENMOB1\_\-REG@{ENMOB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENMOB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENMOB1\_\-REG~CANEN2}\label{ATmega32M1_8h_2829d1f51a00b8d947704f20eb5b89ae}




Definition at line 1039 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENMOB2\_\-REG@{ENMOB2\_\-REG}}
\index{ENMOB2\_\-REG@{ENMOB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENMOB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENMOB2\_\-REG~CANEN2}\label{ATmega32M1_8h_e25ceb2f37d27f40a0241c7a54023d54}




Definition at line 1040 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENMOB3\_\-REG@{ENMOB3\_\-REG}}
\index{ENMOB3\_\-REG@{ENMOB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENMOB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENMOB3\_\-REG~CANEN2}\label{ATmega32M1_8h_49e4d94acca957cd1df3a181c3cb7855}




Definition at line 1041 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENMOB4\_\-REG@{ENMOB4\_\-REG}}
\index{ENMOB4\_\-REG@{ENMOB4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENMOB4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENMOB4\_\-REG~CANEN2}\label{ATmega32M1_8h_155d84521885308f8012aacc0f9a2d3f}




Definition at line 1042 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENMOB5\_\-REG@{ENMOB5\_\-REG}}
\index{ENMOB5\_\-REG@{ENMOB5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENMOB5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENMOB5\_\-REG~CANEN2}\label{ATmega32M1_8h_bf6e41437c5c389f2e4629e793da1c6d}




Definition at line 1043 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENOVRT\_\-REG@{ENOVRT\_\-REG}}
\index{ENOVRT\_\-REG@{ENOVRT\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENOVRT\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENOVRT\_\-REG~CANGIE}\label{ATmega32M1_8h_60fa80828b71b919e7b445edd1462bb3}




Definition at line 622 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENRX\_\-REG@{ENRX\_\-REG}}
\index{ENRX\_\-REG@{ENRX\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENRX\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENRX\_\-REG~CANGIE}\label{ATmega32M1_8h_ccbe2d9a543dd38a4efc2af291e61c5c}




Definition at line 627 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ENTX\_\-REG@{ENTX\_\-REG}}
\index{ENTX\_\-REG@{ENTX\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ENTX\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ENTX\_\-REG~CANGIE}\label{ATmega32M1_8h_529a927513762fa723e4358ffc307646}




Definition at line 626 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ERRP\_\-REG@{ERRP\_\-REG}}
\index{ERRP\_\-REG@{ERRP\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ERRP\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ERRP\_\-REG~CANGSTA}\label{ATmega32M1_8h_43eb70410e557ecc28d85b10bec15ffd}




Definition at line 286 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!EXTRF\_\-REG@{EXTRF\_\-REG}}
\index{EXTRF\_\-REG@{EXTRF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[EXTRF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define EXTRF\_\-REG~MCUSR}\label{ATmega32M1_8h_e620c15a439519ac2da939753266acc5}




Definition at line 852 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!FERG\_\-REG@{FERG\_\-REG}}
\index{FERG\_\-REG@{FERG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[FERG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define FERG\_\-REG~CANGIT}\label{ATmega32M1_8h_9421e6b682f85d88f29b22ab39ac6750}




Definition at line 588 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!FERR\_\-REG@{FERR\_\-REG}}
\index{FERR\_\-REG@{FERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[FERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define FERR\_\-REG~CANSTMOB}\label{ATmega32M1_8h_369da24db36f6c1efba6045940b9e65c}




Definition at line 993 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!FOC0A\_\-REG@{FOC0A\_\-REG}}
\index{FOC0A\_\-REG@{FOC0A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[FOC0A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define FOC0A\_\-REG~TCCR0B}\label{ATmega32M1_8h_5273a16edbe72c0b173bcd9f63fcad5d}




Definition at line 673 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!FOC0B\_\-REG@{FOC0B\_\-REG}}
\index{FOC0B\_\-REG@{FOC0B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[FOC0B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define FOC0B\_\-REG~TCCR0B}\label{ATmega32M1_8h_70b0e0371adb056971724bd8729b2e32}




Definition at line 672 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!FOC1A\_\-REG@{FOC1A\_\-REG}}
\index{FOC1A\_\-REG@{FOC1A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[FOC1A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define FOC1A\_\-REG~TCCR1C}\label{ATmega32M1_8h_a32e14f137d9431fe0e40bb702b9afd3}




Definition at line 518 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!FOC1B\_\-REG@{FOC1B\_\-REG}}
\index{FOC1B\_\-REG@{FOC1B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[FOC1B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define FOC1B\_\-REG~TCCR1C}\label{ATmega32M1_8h_f3dcbc151387e80f44940c02e7cd867d}




Definition at line 517 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR00\_\-REG@{GPIOR00\_\-REG}}
\index{GPIOR00\_\-REG@{GPIOR00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR00\_\-REG~GPIOR0}\label{ATmega32M1_8h_b685813ba32bbaf4420521030d50c037}




Definition at line 567 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR01\_\-REG@{GPIOR01\_\-REG}}
\index{GPIOR01\_\-REG@{GPIOR01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR01\_\-REG~GPIOR0}\label{ATmega32M1_8h_c706e7180a27bf80265fa991c48923da}




Definition at line 568 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR02\_\-REG@{GPIOR02\_\-REG}}
\index{GPIOR02\_\-REG@{GPIOR02\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR02\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR02\_\-REG~GPIOR0}\label{ATmega32M1_8h_e9a044500da3c8fd3b83ee57b753cf5a}




Definition at line 569 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR03\_\-REG@{GPIOR03\_\-REG}}
\index{GPIOR03\_\-REG@{GPIOR03\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR03\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR03\_\-REG~GPIOR0}\label{ATmega32M1_8h_7037df4b8ef967c60655040822116904}




Definition at line 570 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR04\_\-REG@{GPIOR04\_\-REG}}
\index{GPIOR04\_\-REG@{GPIOR04\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR04\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR04\_\-REG~GPIOR0}\label{ATmega32M1_8h_3bcd13cc46c1dad947f4a717886963bd}




Definition at line 571 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR05\_\-REG@{GPIOR05\_\-REG}}
\index{GPIOR05\_\-REG@{GPIOR05\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR05\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR05\_\-REG~GPIOR0}\label{ATmega32M1_8h_d17f1f3640c7c438450e1c6cd83dc416}




Definition at line 572 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR06\_\-REG@{GPIOR06\_\-REG}}
\index{GPIOR06\_\-REG@{GPIOR06\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR06\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR06\_\-REG~GPIOR0}\label{ATmega32M1_8h_34928f33c30d2778bcbd652d3bdc992e}




Definition at line 573 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR07\_\-REG@{GPIOR07\_\-REG}}
\index{GPIOR07\_\-REG@{GPIOR07\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR07\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR07\_\-REG~GPIOR0}\label{ATmega32M1_8h_80bf149d778a818c8b22d0e47d364f6c}




Definition at line 574 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR10\_\-REG@{GPIOR10\_\-REG}}
\index{GPIOR10\_\-REG@{GPIOR10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR10\_\-REG~GPIOR1}\label{ATmega32M1_8h_0c74701f14e731ccfa7947080ec1fd9f}




Definition at line 557 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR11\_\-REG@{GPIOR11\_\-REG}}
\index{GPIOR11\_\-REG@{GPIOR11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR11\_\-REG~GPIOR1}\label{ATmega32M1_8h_c89ae966cc5f650c67a4f64b533b972a}




Definition at line 558 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR12\_\-REG@{GPIOR12\_\-REG}}
\index{GPIOR12\_\-REG@{GPIOR12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR12\_\-REG~GPIOR1}\label{ATmega32M1_8h_7f76dd7c79d2bc02264eddfb83e21f9c}




Definition at line 559 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR13\_\-REG@{GPIOR13\_\-REG}}
\index{GPIOR13\_\-REG@{GPIOR13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR13\_\-REG~GPIOR1}\label{ATmega32M1_8h_59613cf26325e7193f38349c9172edb2}




Definition at line 560 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR14\_\-REG@{GPIOR14\_\-REG}}
\index{GPIOR14\_\-REG@{GPIOR14\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR14\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR14\_\-REG~GPIOR1}\label{ATmega32M1_8h_f6c932c67c1239f8920bea53eefbccd2}




Definition at line 561 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR15\_\-REG@{GPIOR15\_\-REG}}
\index{GPIOR15\_\-REG@{GPIOR15\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR15\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR15\_\-REG~GPIOR1}\label{ATmega32M1_8h_30ca1225d7607c42928f4cad3d965283}




Definition at line 562 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR16\_\-REG@{GPIOR16\_\-REG}}
\index{GPIOR16\_\-REG@{GPIOR16\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR16\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR16\_\-REG~GPIOR1}\label{ATmega32M1_8h_86b974ae70cbc0717a8f7515c3a458c5}




Definition at line 563 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR17\_\-REG@{GPIOR17\_\-REG}}
\index{GPIOR17\_\-REG@{GPIOR17\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR17\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR17\_\-REG~GPIOR1}\label{ATmega32M1_8h_0e49370d23d38b5a3390c338b26209fc}




Definition at line 564 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR20\_\-REG@{GPIOR20\_\-REG}}
\index{GPIOR20\_\-REG@{GPIOR20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR20\_\-REG~GPIOR2}\label{ATmega32M1_8h_3790087c426bd43e2adddb6ecd73e386}




Definition at line 577 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR21\_\-REG@{GPIOR21\_\-REG}}
\index{GPIOR21\_\-REG@{GPIOR21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR21\_\-REG~GPIOR2}\label{ATmega32M1_8h_940062f35eee1065c6303ac7235f559a}




Definition at line 578 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR22\_\-REG@{GPIOR22\_\-REG}}
\index{GPIOR22\_\-REG@{GPIOR22\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR22\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR22\_\-REG~GPIOR2}\label{ATmega32M1_8h_7c436e7420ded2f0613e6641d95b0c52}




Definition at line 579 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR23\_\-REG@{GPIOR23\_\-REG}}
\index{GPIOR23\_\-REG@{GPIOR23\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR23\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR23\_\-REG~GPIOR2}\label{ATmega32M1_8h_df1117d309a043e9c04be45c1b4b77a9}




Definition at line 580 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR24\_\-REG@{GPIOR24\_\-REG}}
\index{GPIOR24\_\-REG@{GPIOR24\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR24\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR24\_\-REG~GPIOR2}\label{ATmega32M1_8h_d44d09cf80aa143ae8524daf27bb7a61}




Definition at line 581 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR25\_\-REG@{GPIOR25\_\-REG}}
\index{GPIOR25\_\-REG@{GPIOR25\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR25\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR25\_\-REG~GPIOR2}\label{ATmega32M1_8h_665dd9b34b86dfda15def8fe104848cc}




Definition at line 582 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR26\_\-REG@{GPIOR26\_\-REG}}
\index{GPIOR26\_\-REG@{GPIOR26\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR26\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR26\_\-REG~GPIOR2}\label{ATmega32M1_8h_b2de6daa35a101d8ce7d3796cf633eed}




Definition at line 583 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!GPIOR27\_\-REG@{GPIOR27\_\-REG}}
\index{GPIOR27\_\-REG@{GPIOR27\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[GPIOR27\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define GPIOR27\_\-REG~GPIOR2}\label{ATmega32M1_8h_104cb3d89f026f59dfb8859ca0208116}




Definition at line 584 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!H\_\-REG@{H\_\-REG}}
\index{H\_\-REG@{H\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[H\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define H\_\-REG~SREG}\label{ATmega32M1_8h_9e7762cfa71109c938bdda8ccfd7a7e8}




Definition at line 913 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!HPMOB0\_\-REG@{HPMOB0\_\-REG}}
\index{HPMOB0\_\-REG@{HPMOB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[HPMOB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define HPMOB0\_\-REG~CANHPMOB}\label{ATmega32M1_8h_c6b7161d1ec010a6ec2300e00cbfd14e}




Definition at line 815 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!HPMOB1\_\-REG@{HPMOB1\_\-REG}}
\index{HPMOB1\_\-REG@{HPMOB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[HPMOB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define HPMOB1\_\-REG~CANHPMOB}\label{ATmega32M1_8h_65cc894b19e150910ddb8a02df835f16}




Definition at line 816 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!HPMOB2\_\-REG@{HPMOB2\_\-REG}}
\index{HPMOB2\_\-REG@{HPMOB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[HPMOB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define HPMOB2\_\-REG~CANHPMOB}\label{ATmega32M1_8h_c92ecabc9761be1385cfc2ffaa68224c}




Definition at line 817 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!HPMOB3\_\-REG@{HPMOB3\_\-REG}}
\index{HPMOB3\_\-REG@{HPMOB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[HPMOB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define HPMOB3\_\-REG~CANHPMOB}\label{ATmega32M1_8h_07903c9e07320df6f3766b5410862e1b}




Definition at line 818 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!I\_\-REG@{I\_\-REG}}
\index{I\_\-REG@{I\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[I\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define I\_\-REG~SREG}\label{ATmega32M1_8h_856b2402264352968c67d30cff7b75ea}




Definition at line 915 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICES1\_\-REG@{ICES1\_\-REG}}
\index{ICES1\_\-REG@{ICES1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICES1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICES1\_\-REG~TCCR1B}\label{ATmega32M1_8h_e92e83fe84adf16f98f3b23b8f914ea8}




Definition at line 1118 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICF1\_\-REG@{ICF1\_\-REG}}
\index{ICF1\_\-REG@{ICF1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICF1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICF1\_\-REG~TIFR1}\label{ATmega32M1_8h_eb06b55a40cf18b321db8df9be5b0ad2}




Definition at line 724 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICIE1\_\-REG@{ICIE1\_\-REG}}
\index{ICIE1\_\-REG@{ICIE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICIE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICIE1\_\-REG~TIMSK1}\label{ATmega32M1_8h_7a00a0ec05842970d9579232d82057e9}




Definition at line 1208 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICNC1\_\-REG@{ICNC1\_\-REG}}
\index{ICNC1\_\-REG@{ICNC1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICNC1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICNC1\_\-REG~TCCR1B}\label{ATmega32M1_8h_667e4c6e04c0c23cdae2a8f287a3d952}




Definition at line 1119 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICP1A\_\-BIT@{ICP1A\_\-BIT}}
\index{ICP1A\_\-BIT@{ICP1A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICP1A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ICP1A\_\-BIT~4}\label{ATmega32M1_8h_56cca498d26bc48096455d1821bf4a53}




Definition at line 1505 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICP1A\_\-PORT@{ICP1A\_\-PORT}}
\index{ICP1A\_\-PORT@{ICP1A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICP1A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ICP1A\_\-PORT~PORTD}\label{ATmega32M1_8h_7a914408ea77f3b133e7c56e73f5cf45}




Definition at line 1504 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICP1B\_\-BIT@{ICP1B\_\-BIT}}
\index{ICP1B\_\-BIT@{ICP1B\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICP1B\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define ICP1B\_\-BIT~3}\label{ATmega32M1_8h_c846800bbce58a144663ff1acd7215ae}




Definition at line 1428 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICP1B\_\-PORT@{ICP1B\_\-PORT}}
\index{ICP1B\_\-PORT@{ICP1B\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICP1B\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define ICP1B\_\-PORT~PORTC}\label{ATmega32M1_8h_0c97ff00ff4d02aa8f35a45876611d5b}




Definition at line 1427 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICPSEL1\_\-REG@{ICPSEL1\_\-REG}}
\index{ICPSEL1\_\-REG@{ICPSEL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICPSEL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICPSEL1\_\-REG~GTCCR}\label{ATmega32M1_8h_cb8f36dbfdd9bf57d6ce3b069133308b}




Definition at line 786 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H0\_\-REG@{ICR1H0\_\-REG}}
\index{ICR1H0\_\-REG@{ICR1H0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H0\_\-REG~ICR1H}\label{ATmega32M1_8h_0dd85b0a7925e38252f0815d981ac84a}




Definition at line 217 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H1\_\-REG@{ICR1H1\_\-REG}}
\index{ICR1H1\_\-REG@{ICR1H1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H1\_\-REG~ICR1H}\label{ATmega32M1_8h_2a414aa65c321e428ec8b47e2a5c2986}




Definition at line 218 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H2\_\-REG@{ICR1H2\_\-REG}}
\index{ICR1H2\_\-REG@{ICR1H2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H2\_\-REG~ICR1H}\label{ATmega32M1_8h_81f995b3e93fcccdc91c17aa36b1e508}




Definition at line 219 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H3\_\-REG@{ICR1H3\_\-REG}}
\index{ICR1H3\_\-REG@{ICR1H3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H3\_\-REG~ICR1H}\label{ATmega32M1_8h_8212333dfb2f3211c3b3c47141b1445f}




Definition at line 220 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H4\_\-REG@{ICR1H4\_\-REG}}
\index{ICR1H4\_\-REG@{ICR1H4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H4\_\-REG~ICR1H}\label{ATmega32M1_8h_d9f8ecadab2e5c7538d5daa95a8a75c9}




Definition at line 221 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H5\_\-REG@{ICR1H5\_\-REG}}
\index{ICR1H5\_\-REG@{ICR1H5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H5\_\-REG~ICR1H}\label{ATmega32M1_8h_7cc78daff77053399d6cfa41097b288c}




Definition at line 222 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H6\_\-REG@{ICR1H6\_\-REG}}
\index{ICR1H6\_\-REG@{ICR1H6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H6\_\-REG~ICR1H}\label{ATmega32M1_8h_cb97e5c5a5919ef84fbf406601351bcd}




Definition at line 223 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1H7\_\-REG@{ICR1H7\_\-REG}}
\index{ICR1H7\_\-REG@{ICR1H7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1H7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1H7\_\-REG~ICR1H}\label{ATmega32M1_8h_014c9ea996b7a18ad73cdb3bd2dccfe2}




Definition at line 224 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L0\_\-REG@{ICR1L0\_\-REG}}
\index{ICR1L0\_\-REG@{ICR1L0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L0\_\-REG~ICR1L}\label{ATmega32M1_8h_e95fa222590af63f1c7a5f70b25faaf3}




Definition at line 227 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L1\_\-REG@{ICR1L1\_\-REG}}
\index{ICR1L1\_\-REG@{ICR1L1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L1\_\-REG~ICR1L}\label{ATmega32M1_8h_27ea7b185d85e278b158ecb430b7e8ef}




Definition at line 228 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L2\_\-REG@{ICR1L2\_\-REG}}
\index{ICR1L2\_\-REG@{ICR1L2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L2\_\-REG~ICR1L}\label{ATmega32M1_8h_6b333223705ca3854f6b25ed303b5953}




Definition at line 229 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L3\_\-REG@{ICR1L3\_\-REG}}
\index{ICR1L3\_\-REG@{ICR1L3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L3\_\-REG~ICR1L}\label{ATmega32M1_8h_a6b87442d23c026c47c3198919dddcbd}




Definition at line 230 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L4\_\-REG@{ICR1L4\_\-REG}}
\index{ICR1L4\_\-REG@{ICR1L4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L4\_\-REG~ICR1L}\label{ATmega32M1_8h_c63ec2126cf0905534aea22a18861df6}




Definition at line 231 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L5\_\-REG@{ICR1L5\_\-REG}}
\index{ICR1L5\_\-REG@{ICR1L5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L5\_\-REG~ICR1L}\label{ATmega32M1_8h_6a3d7c8b564b3652f7c04fd4b6813667}




Definition at line 232 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L6\_\-REG@{ICR1L6\_\-REG}}
\index{ICR1L6\_\-REG@{ICR1L6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L6\_\-REG~ICR1L}\label{ATmega32M1_8h_9968f0ad26bffd020382659080b847ed}




Definition at line 233 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ICR1L7\_\-REG@{ICR1L7\_\-REG}}
\index{ICR1L7\_\-REG@{ICR1L7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ICR1L7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ICR1L7\_\-REG~ICR1L}\label{ATmega32M1_8h_79a04d03d46f919a8a5f7d484242c545}




Definition at line 234 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDE\_\-REG@{IDE\_\-REG}}
\index{IDE\_\-REG@{IDE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDE\_\-REG~CANCDMOB}\label{ATmega32M1_8h_a9920ecf1af5843eedc8855b077d155e}




Definition at line 795 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDEMSK\_\-REG@{IDEMSK\_\-REG}}
\index{IDEMSK\_\-REG@{IDEMSK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDEMSK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDEMSK\_\-REG~CANIDM4}\label{ATmega32M1_8h_9404fede298ea7dacd4b39f18fd44072}




Definition at line 478 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK0\_\-REG@{IDMSK0\_\-REG}}
\index{IDMSK0\_\-REG@{IDMSK0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK0\_\-REG~CANIDM4}\label{ATmega32M1_8h_b5be2738ce28f13ef3587ef4515a7208}




Definition at line 480 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK10\_\-REG@{IDMSK10\_\-REG}}
\index{IDMSK10\_\-REG@{IDMSK10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK10\_\-REG~CANIDM3}\label{ATmega32M1_8h_3b0b925b156bef06e85e1872d3c0a4a6}




Definition at line 463 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK11\_\-REG@{IDMSK11\_\-REG}}
\index{IDMSK11\_\-REG@{IDMSK11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK11\_\-REG~CANIDM3}\label{ATmega32M1_8h_edc6e13d5168bad2dc15dbc39ac082cf}




Definition at line 464 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK12\_\-REG@{IDMSK12\_\-REG}}
\index{IDMSK12\_\-REG@{IDMSK12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK12\_\-REG~CANIDM3}\label{ATmega32M1_8h_7ce4159fa1b0eca76f6819baec811650}




Definition at line 465 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK13\_\-REG@{IDMSK13\_\-REG}}
\index{IDMSK13\_\-REG@{IDMSK13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK13\_\-REG~CANIDM2}\label{ATmega32M1_8h_52dfce339b6b6f04bea03a99e5902a46}




Definition at line 468 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK14\_\-REG@{IDMSK14\_\-REG}}
\index{IDMSK14\_\-REG@{IDMSK14\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK14\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK14\_\-REG~CANIDM2}\label{ATmega32M1_8h_f755a4d90cca400e462b089e6788cbcc}




Definition at line 469 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK15\_\-REG@{IDMSK15\_\-REG}}
\index{IDMSK15\_\-REG@{IDMSK15\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK15\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK15\_\-REG~CANIDM2}\label{ATmega32M1_8h_b7ddc864f6ce9318349026fc3303e60e}




Definition at line 470 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK16\_\-REG@{IDMSK16\_\-REG}}
\index{IDMSK16\_\-REG@{IDMSK16\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK16\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK16\_\-REG~CANIDM2}\label{ATmega32M1_8h_a97ed8dbf176c8d6e8bdca1d2fd29cd4}




Definition at line 471 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK17\_\-REG@{IDMSK17\_\-REG}}
\index{IDMSK17\_\-REG@{IDMSK17\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK17\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK17\_\-REG~CANIDM2}\label{ATmega32M1_8h_532088dca23d067f603f8acf53a768dd}




Definition at line 472 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK18\_\-REG@{IDMSK18\_\-REG}}
\index{IDMSK18\_\-REG@{IDMSK18\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK18\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK18\_\-REG~CANIDM2}\label{ATmega32M1_8h_2f75472b951bfa335dbd535eabdbba62}




Definition at line 473 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK19\_\-REG@{IDMSK19\_\-REG}}
\index{IDMSK19\_\-REG@{IDMSK19\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK19\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK19\_\-REG~CANIDM2}\label{ATmega32M1_8h_a4fd2f7362ce3725d47c91b364c453ed}




Definition at line 474 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK1\_\-REG@{IDMSK1\_\-REG}}
\index{IDMSK1\_\-REG@{IDMSK1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK1\_\-REG~CANIDM4}\label{ATmega32M1_8h_b51e37831a7d5bef5e6e243683bb4860}




Definition at line 481 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK20\_\-REG@{IDMSK20\_\-REG}}
\index{IDMSK20\_\-REG@{IDMSK20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK20\_\-REG~CANIDM2}\label{ATmega32M1_8h_b1cf67ff6a768851df8e3e0cfb7d8e66}




Definition at line 475 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK21\_\-REG@{IDMSK21\_\-REG}}
\index{IDMSK21\_\-REG@{IDMSK21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK21\_\-REG~CANIDM1}\label{ATmega32M1_8h_5750fd8f2b9fc0d97261618ac50e3f2a}




Definition at line 448 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK22\_\-REG@{IDMSK22\_\-REG}}
\index{IDMSK22\_\-REG@{IDMSK22\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK22\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK22\_\-REG~CANIDM1}\label{ATmega32M1_8h_e5588afdc8a9f485a576e6d16f62b007}




Definition at line 449 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK23\_\-REG@{IDMSK23\_\-REG}}
\index{IDMSK23\_\-REG@{IDMSK23\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK23\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK23\_\-REG~CANIDM1}\label{ATmega32M1_8h_65bcf73aa014afbb75e4b75d177a94a9}




Definition at line 450 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK24\_\-REG@{IDMSK24\_\-REG}}
\index{IDMSK24\_\-REG@{IDMSK24\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK24\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK24\_\-REG~CANIDM1}\label{ATmega32M1_8h_a0ddc3d333f9016c3dc04190e077b83e}




Definition at line 451 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK25\_\-REG@{IDMSK25\_\-REG}}
\index{IDMSK25\_\-REG@{IDMSK25\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK25\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK25\_\-REG~CANIDM1}\label{ATmega32M1_8h_ade07711dd10d1093572f1f64f3d55ad}




Definition at line 452 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK26\_\-REG@{IDMSK26\_\-REG}}
\index{IDMSK26\_\-REG@{IDMSK26\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK26\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK26\_\-REG~CANIDM1}\label{ATmega32M1_8h_e499dd1c8ad7857280abfc74653c73f3}




Definition at line 453 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK27\_\-REG@{IDMSK27\_\-REG}}
\index{IDMSK27\_\-REG@{IDMSK27\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK27\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK27\_\-REG~CANIDM1}\label{ATmega32M1_8h_66dd297fa9f225ff204fe4c6621d8b44}




Definition at line 454 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK28\_\-REG@{IDMSK28\_\-REG}}
\index{IDMSK28\_\-REG@{IDMSK28\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK28\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK28\_\-REG~CANIDM1}\label{ATmega32M1_8h_f063de9fddc21de9d63767fbd6a331b2}




Definition at line 455 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK2\_\-REG@{IDMSK2\_\-REG}}
\index{IDMSK2\_\-REG@{IDMSK2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK2\_\-REG~CANIDM4}\label{ATmega32M1_8h_af6e91350291c18c118c28ce5df9f0a3}




Definition at line 482 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK3\_\-REG@{IDMSK3\_\-REG}}
\index{IDMSK3\_\-REG@{IDMSK3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK3\_\-REG~CANIDM4}\label{ATmega32M1_8h_ba2e7a0b4a8bc13922fe3ce0e8235d4a}




Definition at line 483 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK4\_\-REG@{IDMSK4\_\-REG}}
\index{IDMSK4\_\-REG@{IDMSK4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK4\_\-REG~CANIDM4}\label{ATmega32M1_8h_393578bfdd35a686cb9acc1ca025ebda}




Definition at line 484 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK5\_\-REG@{IDMSK5\_\-REG}}
\index{IDMSK5\_\-REG@{IDMSK5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK5\_\-REG~CANIDM3}\label{ATmega32M1_8h_9b3116ec859961056bb8d3a0abb75d37}




Definition at line 458 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK6\_\-REG@{IDMSK6\_\-REG}}
\index{IDMSK6\_\-REG@{IDMSK6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK6\_\-REG~CANIDM3}\label{ATmega32M1_8h_eb3b82b4327249d79def24efcc2d6b1f}




Definition at line 459 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK7\_\-REG@{IDMSK7\_\-REG}}
\index{IDMSK7\_\-REG@{IDMSK7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK7\_\-REG~CANIDM3}\label{ATmega32M1_8h_6aaee0fa68971d74096fe845c177e891}




Definition at line 460 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK8\_\-REG@{IDMSK8\_\-REG}}
\index{IDMSK8\_\-REG@{IDMSK8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK8\_\-REG~CANIDM3}\label{ATmega32M1_8h_1a865eeaba115122176a9a36148639d6}




Definition at line 461 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDMSK9\_\-REG@{IDMSK9\_\-REG}}
\index{IDMSK9\_\-REG@{IDMSK9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDMSK9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDMSK9\_\-REG~CANIDM3}\label{ATmega32M1_8h_b93f0f07c9dea044798c797b92062420}




Definition at line 462 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT0\_\-REG@{IDT0\_\-REG}}
\index{IDT0\_\-REG@{IDT0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT0\_\-REG~CANIDT4}\label{ATmega32M1_8h_dae2c99bb7e34af43ee764f7e8315823}




Definition at line 730 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT10\_\-REG@{IDT10\_\-REG}}
\index{IDT10\_\-REG@{IDT10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT10\_\-REG~CANIDT3}\label{ATmega32M1_8h_c7de9f6a94593e0d46c97c395b8aa426}




Definition at line 762 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT11\_\-REG@{IDT11\_\-REG}}
\index{IDT11\_\-REG@{IDT11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT11\_\-REG~CANIDT3}\label{ATmega32M1_8h_c84fd5fa69956c9126b135e7ab2eef1e}




Definition at line 763 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT12\_\-REG@{IDT12\_\-REG}}
\index{IDT12\_\-REG@{IDT12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT12\_\-REG~CANIDT3}\label{ATmega32M1_8h_93cfe9e786875366583d375f930c6733}




Definition at line 764 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT13\_\-REG@{IDT13\_\-REG}}
\index{IDT13\_\-REG@{IDT13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT13\_\-REG~CANIDT2}\label{ATmega32M1_8h_1295e6e96ccd05034f20ce5b05768bb4}




Definition at line 747 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT14\_\-REG@{IDT14\_\-REG}}
\index{IDT14\_\-REG@{IDT14\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT14\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT14\_\-REG~CANIDT2}\label{ATmega32M1_8h_d55c6ef576227306a5cc67d07b177c80}




Definition at line 748 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT15\_\-REG@{IDT15\_\-REG}}
\index{IDT15\_\-REG@{IDT15\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT15\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT15\_\-REG~CANIDT2}\label{ATmega32M1_8h_89f188ec183f0dc3fc4c92b2e5f08c85}




Definition at line 749 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT16\_\-REG@{IDT16\_\-REG}}
\index{IDT16\_\-REG@{IDT16\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT16\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT16\_\-REG~CANIDT2}\label{ATmega32M1_8h_d70c66aac6e76f07d79a9c8736a62213}




Definition at line 750 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT17\_\-REG@{IDT17\_\-REG}}
\index{IDT17\_\-REG@{IDT17\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT17\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT17\_\-REG~CANIDT2}\label{ATmega32M1_8h_e62220b4dee7e05752e3a1907c63bd86}




Definition at line 751 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT18\_\-REG@{IDT18\_\-REG}}
\index{IDT18\_\-REG@{IDT18\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT18\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT18\_\-REG~CANIDT2}\label{ATmega32M1_8h_ad6cb3bb885ed00664d43644f7462c3b}




Definition at line 752 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT19\_\-REG@{IDT19\_\-REG}}
\index{IDT19\_\-REG@{IDT19\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT19\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT19\_\-REG~CANIDT2}\label{ATmega32M1_8h_01c409ee9d914cf02bb5e40b3929862c}




Definition at line 753 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT1\_\-REG@{IDT1\_\-REG}}
\index{IDT1\_\-REG@{IDT1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT1\_\-REG~CANIDT4}\label{ATmega32M1_8h_2807d0fc95414dbe5365a49fc3bc7bcf}




Definition at line 731 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT20\_\-REG@{IDT20\_\-REG}}
\index{IDT20\_\-REG@{IDT20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT20\_\-REG~CANIDT2}\label{ATmega32M1_8h_0401439faa308885628723eb62727347}




Definition at line 754 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT21\_\-REG@{IDT21\_\-REG}}
\index{IDT21\_\-REG@{IDT21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT21\_\-REG~CANIDT1}\label{ATmega32M1_8h_a8958c6ddabc91f0133356196a3c4461}




Definition at line 767 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT22\_\-REG@{IDT22\_\-REG}}
\index{IDT22\_\-REG@{IDT22\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT22\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT22\_\-REG~CANIDT1}\label{ATmega32M1_8h_6000426ab8b332f0cf441f72db6426a6}




Definition at line 768 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT23\_\-REG@{IDT23\_\-REG}}
\index{IDT23\_\-REG@{IDT23\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT23\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT23\_\-REG~CANIDT1}\label{ATmega32M1_8h_7fb715fe7d7234044231f397a7b515ff}




Definition at line 769 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT24\_\-REG@{IDT24\_\-REG}}
\index{IDT24\_\-REG@{IDT24\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT24\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT24\_\-REG~CANIDT1}\label{ATmega32M1_8h_83441339722ca3da0ebd3a0afd9e2a13}




Definition at line 770 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT25\_\-REG@{IDT25\_\-REG}}
\index{IDT25\_\-REG@{IDT25\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT25\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT25\_\-REG~CANIDT1}\label{ATmega32M1_8h_669788d96eb2bc86a06e52faa643b47f}




Definition at line 771 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT26\_\-REG@{IDT26\_\-REG}}
\index{IDT26\_\-REG@{IDT26\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT26\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT26\_\-REG~CANIDT1}\label{ATmega32M1_8h_1e81a987096dca3e32fa9232d61e0da8}




Definition at line 772 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT27\_\-REG@{IDT27\_\-REG}}
\index{IDT27\_\-REG@{IDT27\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT27\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT27\_\-REG~CANIDT1}\label{ATmega32M1_8h_2172a8f475012da5c75ca05eb5d7f55b}




Definition at line 773 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT28\_\-REG@{IDT28\_\-REG}}
\index{IDT28\_\-REG@{IDT28\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT28\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT28\_\-REG~CANIDT1}\label{ATmega32M1_8h_f23d2211d84bfcb8199b02c4c01996c4}




Definition at line 774 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT2\_\-REG@{IDT2\_\-REG}}
\index{IDT2\_\-REG@{IDT2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT2\_\-REG~CANIDT4}\label{ATmega32M1_8h_5b06665e6f7d4186152b40c514f58a16}




Definition at line 732 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT3\_\-REG@{IDT3\_\-REG}}
\index{IDT3\_\-REG@{IDT3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT3\_\-REG~CANIDT4}\label{ATmega32M1_8h_275cf8ff802040c81f6af18f79f8e1e8}




Definition at line 733 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT4\_\-REG@{IDT4\_\-REG}}
\index{IDT4\_\-REG@{IDT4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT4\_\-REG~CANIDT4}\label{ATmega32M1_8h_e2edcdc070fdbb24fbe7d2e59d88e579}




Definition at line 734 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT5\_\-REG@{IDT5\_\-REG}}
\index{IDT5\_\-REG@{IDT5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT5\_\-REG~CANIDT3}\label{ATmega32M1_8h_a489af3458d595aea38e9a1917a360ed}




Definition at line 757 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT6\_\-REG@{IDT6\_\-REG}}
\index{IDT6\_\-REG@{IDT6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT6\_\-REG~CANIDT3}\label{ATmega32M1_8h_5424d991c260d00cbfe5a992d69894fc}




Definition at line 758 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT7\_\-REG@{IDT7\_\-REG}}
\index{IDT7\_\-REG@{IDT7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT7\_\-REG~CANIDT3}\label{ATmega32M1_8h_4711931948eead507a5477489dc82764}




Definition at line 759 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT8\_\-REG@{IDT8\_\-REG}}
\index{IDT8\_\-REG@{IDT8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT8\_\-REG~CANIDT3}\label{ATmega32M1_8h_b27ec25037c978ed20e173c8f60a79c9}




Definition at line 760 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IDT9\_\-REG@{IDT9\_\-REG}}
\index{IDT9\_\-REG@{IDT9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IDT9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IDT9\_\-REG~CANIDT3}\label{ATmega32M1_8h_bb09bd1bc90a1cdf762e1d72c9d696db}




Definition at line 761 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IEMOB0\_\-REG@{IEMOB0\_\-REG}}
\index{IEMOB0\_\-REG@{IEMOB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IEMOB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IEMOB0\_\-REG~CANIE2}\label{ATmega32M1_8h_6ee27b3b84fe2bde57ca0adcb679fd89}




Definition at line 642 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IEMOB1\_\-REG@{IEMOB1\_\-REG}}
\index{IEMOB1\_\-REG@{IEMOB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IEMOB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IEMOB1\_\-REG~CANIE2}\label{ATmega32M1_8h_15dd00dfff10aeff0e4dbcffb8e4f4a2}




Definition at line 643 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IEMOB2\_\-REG@{IEMOB2\_\-REG}}
\index{IEMOB2\_\-REG@{IEMOB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IEMOB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IEMOB2\_\-REG~CANIE2}\label{ATmega32M1_8h_791416cbf4942d3cddc2ed317f033b75}




Definition at line 644 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IEMOB3\_\-REG@{IEMOB3\_\-REG}}
\index{IEMOB3\_\-REG@{IEMOB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IEMOB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IEMOB3\_\-REG~CANIE2}\label{ATmega32M1_8h_b7f984e8215ef50520a008ea9a2a594c}




Definition at line 645 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IEMOB4\_\-REG@{IEMOB4\_\-REG}}
\index{IEMOB4\_\-REG@{IEMOB4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IEMOB4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IEMOB4\_\-REG~CANIE2}\label{ATmega32M1_8h_6ef0f66b3b14ad29ee8e10c58195319d}




Definition at line 646 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IEMOB5\_\-REG@{IEMOB5\_\-REG}}
\index{IEMOB5\_\-REG@{IEMOB5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IEMOB5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IEMOB5\_\-REG~CANIE2}\label{ATmega32M1_8h_adde78b5da31a0134c06751601ac1423}




Definition at line 647 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INDX0\_\-REG@{INDX0\_\-REG}}
\index{INDX0\_\-REG@{INDX0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INDX0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INDX0\_\-REG~CANPAGE}\label{ATmega32M1_8h_4f8c0cbdf398933e8af2668eb285921a}




Definition at line 358 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INDX1\_\-REG@{INDX1\_\-REG}}
\index{INDX1\_\-REG@{INDX1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INDX1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INDX1\_\-REG~CANPAGE}\label{ATmega32M1_8h_20856b38a0e069df7ab24859b6edb6b4}




Definition at line 359 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INDX2\_\-REG@{INDX2\_\-REG}}
\index{INDX2\_\-REG@{INDX2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INDX2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INDX2\_\-REG~CANPAGE}\label{ATmega32M1_8h_446dac9fae09acaf209764c500c100b1}




Definition at line 360 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT0\_\-BIT@{INT0\_\-BIT}}
\index{INT0\_\-BIT@{INT0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT0\_\-BIT~6}\label{ATmega32M1_8h_5d004e5a830a09b875a030e98a40a55b}




Definition at line 1523 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT0\_\-PORT@{INT0\_\-PORT}}
\index{INT0\_\-PORT@{INT0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT0\_\-PORT~PORTD}\label{ATmega32M1_8h_dc981fa047fd68da334581984c22269f}




Definition at line 1522 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT0\_\-REG@{INT0\_\-REG}}
\index{INT0\_\-REG@{INT0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INT0\_\-REG~EIMSK}\label{ATmega32M1_8h_ef41b7ee03276d4f5fcd2255aba0dce4}




Definition at line 368 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT1\_\-BIT@{INT1\_\-BIT}}
\index{INT1\_\-BIT@{INT1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT1\_\-BIT~2}\label{ATmega32M1_8h_087cf0a65af1e5b32ce8c2a7104f97bd}




Definition at line 1357 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT1\_\-PORT@{INT1\_\-PORT}}
\index{INT1\_\-PORT@{INT1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT1\_\-PORT~PORTB}\label{ATmega32M1_8h_f96062a0df1453b55f3925974436e531}




Definition at line 1356 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT1\_\-REG@{INT1\_\-REG}}
\index{INT1\_\-REG@{INT1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INT1\_\-REG~EIMSK}\label{ATmega32M1_8h_ed8a95911748ccc51f86338edd2a850c}




Definition at line 369 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT2\_\-BIT@{INT2\_\-BIT}}
\index{INT2\_\-BIT@{INT2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT2\_\-BIT~5}\label{ATmega32M1_8h_76e97c2312ea89a01323b87eb5258ee7}




Definition at line 1376 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT2\_\-PORT@{INT2\_\-PORT}}
\index{INT2\_\-PORT@{INT2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT2\_\-PORT~PORTB}\label{ATmega32M1_8h_9b2ca3d6eabbe1d6e038dc0c983b0460}




Definition at line 1375 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT2\_\-REG@{INT2\_\-REG}}
\index{INT2\_\-REG@{INT2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INT2\_\-REG~EIMSK}\label{ATmega32M1_8h_ea735ad7d48b20943b32340fa26a4073}




Definition at line 370 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT3\_\-BIT@{INT3\_\-BIT}}
\index{INT3\_\-BIT@{INT3\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT3\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT3\_\-BIT~0}\label{ATmega32M1_8h_4e013943ba14f67e49e123947b93df62}




Definition at line 1401 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT3\_\-PORT@{INT3\_\-PORT}}
\index{INT3\_\-PORT@{INT3\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT3\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define INT3\_\-PORT~PORTC}\label{ATmega32M1_8h_638c53e478ed12e1f201297c6d307243}




Definition at line 1400 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INT3\_\-REG@{INT3\_\-REG}}
\index{INT3\_\-REG@{INT3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INT3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INT3\_\-REG~EIMSK}\label{ATmega32M1_8h_f47858a0ab6e747d696d3d34b2f8b657}




Definition at line 371 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INTF0\_\-REG@{INTF0\_\-REG}}
\index{INTF0\_\-REG@{INTF0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INTF0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INTF0\_\-REG~EIFR}\label{ATmega32M1_8h_c8eea570a562240195a8d71daa36a15a}




Definition at line 986 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INTF1\_\-REG@{INTF1\_\-REG}}
\index{INTF1\_\-REG@{INTF1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INTF1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INTF1\_\-REG~EIFR}\label{ATmega32M1_8h_18326e0f6547e43792de1ed122ee4382}




Definition at line 987 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INTF2\_\-REG@{INTF2\_\-REG}}
\index{INTF2\_\-REG@{INTF2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INTF2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INTF2\_\-REG~EIFR}\label{ATmega32M1_8h_05ff50f0cf4c490f7b45a9506f07c116}




Definition at line 988 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!INTF3\_\-REG@{INTF3\_\-REG}}
\index{INTF3\_\-REG@{INTF3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[INTF3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define INTF3\_\-REG~EIFR}\label{ATmega32M1_8h_2bc3a324ee02d7ebeb0767ded371bd6b}




Definition at line 989 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC00\_\-REG@{ISC00\_\-REG}}
\index{ISC00\_\-REG@{ISC00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC00\_\-REG~EICRA}\label{ATmega32M1_8h_21c52d8f7ccc0b73261c2871950dec5f}




Definition at line 380 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC01\_\-REG@{ISC01\_\-REG}}
\index{ISC01\_\-REG@{ISC01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC01\_\-REG~EICRA}\label{ATmega32M1_8h_1d3247e568986e0a910394086a1aa8a8}




Definition at line 381 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC10\_\-REG@{ISC10\_\-REG}}
\index{ISC10\_\-REG@{ISC10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC10\_\-REG~EICRA}\label{ATmega32M1_8h_d8fcec19bf04f6c2fdd03b92511928b8}




Definition at line 382 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC11\_\-REG@{ISC11\_\-REG}}
\index{ISC11\_\-REG@{ISC11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC11\_\-REG~EICRA}\label{ATmega32M1_8h_dcec47801cf8ca8953ebc068cfa097c8}




Definition at line 383 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC20\_\-REG@{ISC20\_\-REG}}
\index{ISC20\_\-REG@{ISC20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC20\_\-REG~EICRA}\label{ATmega32M1_8h_07ddc6fbbaea79b0d8e327399ace7343}




Definition at line 384 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC21\_\-REG@{ISC21\_\-REG}}
\index{ISC21\_\-REG@{ISC21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC21\_\-REG~EICRA}\label{ATmega32M1_8h_1c4f80e5ee5e9ff648be2f1378827af4}




Definition at line 385 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC30\_\-REG@{ISC30\_\-REG}}
\index{ISC30\_\-REG@{ISC30\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC30\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC30\_\-REG~EICRA}\label{ATmega32M1_8h_708c40b174145e7a0bdbf82c42413426}




Definition at line 386 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISC31\_\-REG@{ISC31\_\-REG}}
\index{ISC31\_\-REG@{ISC31\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISC31\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISC31\_\-REG~EICRA}\label{ATmega32M1_8h_3947671fbfd87c7b6fe0372940cdccd0}




Definition at line 387 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!ISRCEN\_\-REG@{ISRCEN\_\-REG}}
\index{ISRCEN\_\-REG@{ISRCEN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[ISRCEN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define ISRCEN\_\-REG~ADCSRB}\label{ATmega32M1_8h_74d540962c738ef42f83830abc4db29b}




Definition at line 1051 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IVCE\_\-REG@{IVCE\_\-REG}}
\index{IVCE\_\-REG@{IVCE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IVCE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IVCE\_\-REG~MCUCR}\label{ATmega32M1_8h_a2d0b2fab1e834745137c45cdc990652}




Definition at line 970 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!IVSEL\_\-REG@{IVSEL\_\-REG}}
\index{IVSEL\_\-REG@{IVSEL\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[IVSEL\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define IVSEL\_\-REG~MCUCR}\label{ATmega32M1_8h_4b1c656675f122c04630fd0059be6a42}




Definition at line 971 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LABORT\_\-REG@{LABORT\_\-REG}}
\index{LABORT\_\-REG@{LABORT\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LABORT\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LABORT\_\-REG~LINERR}\label{ATmega32M1_8h_ee8b1c19d7883b4dd2f52bd0d26f27b6}




Definition at line 613 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LAINC\_\-REG@{LAINC\_\-REG}}
\index{LAINC\_\-REG@{LAINC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LAINC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LAINC\_\-REG~LINSEL}\label{ATmega32M1_8h_75f44ded887a5e31020572cee570b5e1}




Definition at line 177 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBERR\_\-REG@{LBERR\_\-REG}}
\index{LBERR\_\-REG@{LBERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBERR\_\-REG~LINERR}\label{ATmega32M1_8h_dcb164eaf3d5bfad9126614432e640ca}




Definition at line 606 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBT0\_\-REG@{LBT0\_\-REG}}
\index{LBT0\_\-REG@{LBT0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBT0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBT0\_\-REG~LINBTR}\label{ATmega32M1_8h_443906bc714352393d66a11de2c36e7b}




Definition at line 109 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBT1\_\-REG@{LBT1\_\-REG}}
\index{LBT1\_\-REG@{LBT1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBT1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBT1\_\-REG~LINBTR}\label{ATmega32M1_8h_dfe57e246790cdbc7e3980d0e047807f}




Definition at line 110 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBT2\_\-REG@{LBT2\_\-REG}}
\index{LBT2\_\-REG@{LBT2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBT2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBT2\_\-REG~LINBTR}\label{ATmega32M1_8h_20857cdb038a9908fc4ac1b5659bfca5}




Definition at line 111 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBT3\_\-REG@{LBT3\_\-REG}}
\index{LBT3\_\-REG@{LBT3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBT3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBT3\_\-REG~LINBTR}\label{ATmega32M1_8h_13a9bc689fe893524d750c93ba682892}




Definition at line 112 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBT4\_\-REG@{LBT4\_\-REG}}
\index{LBT4\_\-REG@{LBT4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBT4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBT4\_\-REG~LINBTR}\label{ATmega32M1_8h_9e855ecad3983ef63458e70991379e91}




Definition at line 113 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBT5\_\-REG@{LBT5\_\-REG}}
\index{LBT5\_\-REG@{LBT5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBT5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBT5\_\-REG~LINBTR}\label{ATmega32M1_8h_eb2bca58ae1f01e00b882fadd4bb04bb}




Definition at line 114 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LBUSY\_\-REG@{LBUSY\_\-REG}}
\index{LBUSY\_\-REG@{LBUSY\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LBUSY\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LBUSY\_\-REG~LINSIR}\label{ATmega32M1_8h_b0c58fdd6c2169b6fbf54d211cff9fb8}




Definition at line 1012 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LCERR\_\-REG@{LCERR\_\-REG}}
\index{LCERR\_\-REG@{LCERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LCERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LCERR\_\-REG~LINERR}\label{ATmega32M1_8h_a54c562a706c8ece52b9f335a2cb4dce}




Definition at line 607 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LCMD0\_\-REG@{LCMD0\_\-REG}}
\index{LCMD0\_\-REG@{LCMD0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LCMD0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LCMD0\_\-REG~LINCR}\label{ATmega32M1_8h_628e5ea3ab05d6e4c1ef0b2173619069}




Definition at line 180 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LCMD1\_\-REG@{LCMD1\_\-REG}}
\index{LCMD1\_\-REG@{LCMD1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LCMD1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LCMD1\_\-REG~LINCR}\label{ATmega32M1_8h_a362ea0381486ced43759830d2408fcf}




Definition at line 181 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LCMD2\_\-REG@{LCMD2\_\-REG}}
\index{LCMD2\_\-REG@{LCMD2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LCMD2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LCMD2\_\-REG~LINCR}\label{ATmega32M1_8h_76e5dd81399016f23427c36f9018de36}




Definition at line 182 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LCONF0\_\-REG@{LCONF0\_\-REG}}
\index{LCONF0\_\-REG@{LCONF0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LCONF0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LCONF0\_\-REG~LINCR}\label{ATmega32M1_8h_80f48b47b20b5deca417e3ae79868f9b}




Definition at line 184 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LCONF1\_\-REG@{LCONF1\_\-REG}}
\index{LCONF1\_\-REG@{LCONF1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LCONF1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LCONF1\_\-REG~LINCR}\label{ATmega32M1_8h_639cc72162f356dff404aa61f6807f3d}




Definition at line 185 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA0\_\-REG@{LDATA0\_\-REG}}
\index{LDATA0\_\-REG@{LDATA0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA0\_\-REG~LINDAT}\label{ATmega32M1_8h_47d4f5efd2665f2b4189bf2639b66cfa}




Definition at line 918 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA1\_\-REG@{LDATA1\_\-REG}}
\index{LDATA1\_\-REG@{LDATA1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA1\_\-REG~LINDAT}\label{ATmega32M1_8h_cd85cc17a2cc0cdb8837c442ba7f7a9c}




Definition at line 919 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA2\_\-REG@{LDATA2\_\-REG}}
\index{LDATA2\_\-REG@{LDATA2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA2\_\-REG~LINDAT}\label{ATmega32M1_8h_09e152c5379e91bbe1a6c4728032f32f}




Definition at line 920 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA3\_\-REG@{LDATA3\_\-REG}}
\index{LDATA3\_\-REG@{LDATA3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA3\_\-REG~LINDAT}\label{ATmega32M1_8h_ccca93de22edc51438b370d1f35f881e}




Definition at line 921 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA4\_\-REG@{LDATA4\_\-REG}}
\index{LDATA4\_\-REG@{LDATA4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA4\_\-REG~LINDAT}\label{ATmega32M1_8h_cae6a433fdb98ae09f74a96c4fc5a8df}




Definition at line 922 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA5\_\-REG@{LDATA5\_\-REG}}
\index{LDATA5\_\-REG@{LDATA5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA5\_\-REG~LINDAT}\label{ATmega32M1_8h_7113c98ab0f4d5d9bfc77823bc87cea4}




Definition at line 923 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA6\_\-REG@{LDATA6\_\-REG}}
\index{LDATA6\_\-REG@{LDATA6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA6\_\-REG~LINDAT}\label{ATmega32M1_8h_15ff1beb79b282a4b61fe612e8cf5d3b}




Definition at line 924 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDATA7\_\-REG@{LDATA7\_\-REG}}
\index{LDATA7\_\-REG@{LDATA7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDATA7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDATA7\_\-REG~LINDAT}\label{ATmega32M1_8h_8c433b76c513c425dbed117c8f76f6c6}




Definition at line 925 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDISR\_\-REG@{LDISR\_\-REG}}
\index{LDISR\_\-REG@{LDISR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDISR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDISR\_\-REG~LINBTR}\label{ATmega32M1_8h_8748fc9200a0d3f2e30d82a01265ed35}




Definition at line 115 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV0\_\-REG@{LDIV0\_\-REG}}
\index{LDIV0\_\-REG@{LDIV0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV0\_\-REG~LINBRRL}\label{ATmega32M1_8h_ebf65f7e7b374eaa273a2bd4533ff15c}




Definition at line 266 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV10\_\-REG@{LDIV10\_\-REG}}
\index{LDIV10\_\-REG@{LDIV10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV10\_\-REG~LINBRRH}\label{ATmega32M1_8h_7134bd7e85695a924507249abb4d6289}




Definition at line 282 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV11\_\-REG@{LDIV11\_\-REG}}
\index{LDIV11\_\-REG@{LDIV11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV11\_\-REG~LINBRRH}\label{ATmega32M1_8h_64005fdbf40af9b8335adf05d35a6c5a}




Definition at line 283 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV1\_\-REG@{LDIV1\_\-REG}}
\index{LDIV1\_\-REG@{LDIV1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV1\_\-REG~LINBRRL}\label{ATmega32M1_8h_8925693658936bf80cd6c3d18843a074}




Definition at line 267 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV2\_\-REG@{LDIV2\_\-REG}}
\index{LDIV2\_\-REG@{LDIV2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV2\_\-REG~LINBRRL}\label{ATmega32M1_8h_2c1685c869b99e1331457d1ec307935e}




Definition at line 268 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV3\_\-REG@{LDIV3\_\-REG}}
\index{LDIV3\_\-REG@{LDIV3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV3\_\-REG~LINBRRL}\label{ATmega32M1_8h_ba93d14842266c71a03e431a47f63c39}




Definition at line 269 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV4\_\-REG@{LDIV4\_\-REG}}
\index{LDIV4\_\-REG@{LDIV4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV4\_\-REG~LINBRRL}\label{ATmega32M1_8h_056d29aafb4dfdce5bdb7e497745c5a1}




Definition at line 270 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV5\_\-REG@{LDIV5\_\-REG}}
\index{LDIV5\_\-REG@{LDIV5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV5\_\-REG~LINBRRL}\label{ATmega32M1_8h_5507bed0ce8fe0cdb4fd18d8f8c31117}




Definition at line 271 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV6\_\-REG@{LDIV6\_\-REG}}
\index{LDIV6\_\-REG@{LDIV6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV6\_\-REG~LINBRRL}\label{ATmega32M1_8h_359a49c6c09cb921f923f45fc94112a9}




Definition at line 272 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV7\_\-REG@{LDIV7\_\-REG}}
\index{LDIV7\_\-REG@{LDIV7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV7\_\-REG~LINBRRL}\label{ATmega32M1_8h_f2e7aab70c29d58275494aa13282de46}




Definition at line 273 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV8\_\-REG@{LDIV8\_\-REG}}
\index{LDIV8\_\-REG@{LDIV8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV8\_\-REG~LINBRRH}\label{ATmega32M1_8h_d6afd60e683990790b93183dfc9b7a70}




Definition at line 280 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LDIV9\_\-REG@{LDIV9\_\-REG}}
\index{LDIV9\_\-REG@{LDIV9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LDIV9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LDIV9\_\-REG~LINBRRH}\label{ATmega32M1_8h_8321788cb4a78f55a1918ef4e25126fc}




Definition at line 281 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LENA\_\-REG@{LENA\_\-REG}}
\index{LENA\_\-REG@{LENA\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LENA\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LENA\_\-REG~LINCR}\label{ATmega32M1_8h_52123b3371340e2d3232152a35d5ca58}




Definition at line 183 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LENERR\_\-REG@{LENERR\_\-REG}}
\index{LENERR\_\-REG@{LENERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LENERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LENERR\_\-REG~LINENIR}\label{ATmega32M1_8h_2633a7eb2faf91bbd3e3bab59e9b506b}




Definition at line 377 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LENIDOK\_\-REG@{LENIDOK\_\-REG}}
\index{LENIDOK\_\-REG@{LENIDOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LENIDOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LENIDOK\_\-REG~LINENIR}\label{ATmega32M1_8h_266299910dd57ca3b39c4b264b19d241}




Definition at line 376 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LENRXOK\_\-REG@{LENRXOK\_\-REG}}
\index{LENRXOK\_\-REG@{LENRXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LENRXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LENRXOK\_\-REG~LINENIR}\label{ATmega32M1_8h_7bd3843921837d2f987589a7023d3f90}




Definition at line 374 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LENTXOK\_\-REG@{LENTXOK\_\-REG}}
\index{LENTXOK\_\-REG@{LENTXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LENTXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LENTXOK\_\-REG~LINENIR}\label{ATmega32M1_8h_caced183e5471f8c69abd5becacf1aef}




Definition at line 375 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LERR\_\-REG@{LERR\_\-REG}}
\index{LERR\_\-REG@{LERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LERR\_\-REG~LINSIR}\label{ATmega32M1_8h_d9cee22872f09bbc09ccf6319b702a97}




Definition at line 1011 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LFERR\_\-REG@{LFERR\_\-REG}}
\index{LFERR\_\-REG@{LFERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LFERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LFERR\_\-REG~LINERR}\label{ATmega32M1_8h_a665063777ac7acdd0678706d78468a2}




Definition at line 610 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LID0\_\-REG@{LID0\_\-REG}}
\index{LID0\_\-REG@{LID0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LID0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LID0\_\-REG~LINIDR}\label{ATmega32M1_8h_8b267b58788c4072c783c4248e63af2b}




Definition at line 128 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LID1\_\-REG@{LID1\_\-REG}}
\index{LID1\_\-REG@{LID1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LID1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LID1\_\-REG~LINIDR}\label{ATmega32M1_8h_016519b977f1ce81f22b2a61c7cf2eaf}




Definition at line 129 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LID2\_\-REG@{LID2\_\-REG}}
\index{LID2\_\-REG@{LID2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LID2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LID2\_\-REG~LINIDR}\label{ATmega32M1_8h_7f70a785d02d5306b77bbc67c4174282}




Definition at line 130 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LID3\_\-REG@{LID3\_\-REG}}
\index{LID3\_\-REG@{LID3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LID3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LID3\_\-REG~LINIDR}\label{ATmega32M1_8h_19d8f45a9f2073f73df2b66558291224}




Definition at line 131 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LID4\_\-REG@{LID4\_\-REG}}
\index{LID4\_\-REG@{LID4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LID4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LID4\_\-REG~LINIDR}\label{ATmega32M1_8h_613066ba0ee6bef2013ba1311850ca46}




Definition at line 132 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LID5\_\-REG@{LID5\_\-REG}}
\index{LID5\_\-REG@{LID5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LID5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LID5\_\-REG~LINIDR}\label{ATmega32M1_8h_17037004c7f3bad208d10b31fccecfab}




Definition at line 133 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LIDOK\_\-REG@{LIDOK\_\-REG}}
\index{LIDOK\_\-REG@{LIDOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LIDOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LIDOK\_\-REG~LINSIR}\label{ATmega32M1_8h_0e7dbcd90487818e078b37579a30be7d}




Definition at line 1010 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LIDST0\_\-REG@{LIDST0\_\-REG}}
\index{LIDST0\_\-REG@{LIDST0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LIDST0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LIDST0\_\-REG~LINSIR}\label{ATmega32M1_8h_c9ba1fe3bd497b66ded331f9a1d260f9}




Definition at line 1013 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LIDST1\_\-REG@{LIDST1\_\-REG}}
\index{LIDST1\_\-REG@{LIDST1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LIDST1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LIDST1\_\-REG~LINSIR}\label{ATmega32M1_8h_e943620d39cd8f9b7c70f4145badee99}




Definition at line 1014 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LIDST2\_\-REG@{LIDST2\_\-REG}}
\index{LIDST2\_\-REG@{LIDST2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LIDST2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LIDST2\_\-REG~LINSIR}\label{ATmega32M1_8h_c744781da4e305d016cf72c89344a6b7}




Definition at line 1015 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LIN13\_\-REG@{LIN13\_\-REG}}
\index{LIN13\_\-REG@{LIN13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LIN13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LIN13\_\-REG~LINCR}\label{ATmega32M1_8h_b13795832444c2a4ec5faa99ef69449b}




Definition at line 186 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LINDX0\_\-REG@{LINDX0\_\-REG}}
\index{LINDX0\_\-REG@{LINDX0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LINDX0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LINDX0\_\-REG~LINSEL}\label{ATmega32M1_8h_3b56eedba876f2a6ef0ae0c242d06d7d}




Definition at line 174 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LINDX1\_\-REG@{LINDX1\_\-REG}}
\index{LINDX1\_\-REG@{LINDX1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LINDX1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LINDX1\_\-REG~LINSEL}\label{ATmega32M1_8h_1872c426370288e31b2ac967e00d5a44}




Definition at line 175 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LINDX2\_\-REG@{LINDX2\_\-REG}}
\index{LINDX2\_\-REG@{LINDX2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LINDX2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LINDX2\_\-REG~LINSEL}\label{ATmega32M1_8h_f26a9365fe0448d87bdcb09f1bd045b0}




Definition at line 176 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LISTEN\_\-REG@{LISTEN\_\-REG}}
\index{LISTEN\_\-REG@{LISTEN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LISTEN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LISTEN\_\-REG~CANGCON}\label{ATmega32M1_8h_6edcc00a6995a3a3add481a0246516d5}




Definition at line 297 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LOVERR\_\-REG@{LOVERR\_\-REG}}
\index{LOVERR\_\-REG@{LOVERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LOVERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LOVERR\_\-REG~LINERR}\label{ATmega32M1_8h_11b3bd93f2ca088265fcb075d5bdbf18}




Definition at line 611 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LP0\_\-REG@{LP0\_\-REG}}
\index{LP0\_\-REG@{LP0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LP0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LP0\_\-REG~LINIDR}\label{ATmega32M1_8h_6e0e4125ed3430b43d406140cb90cd80}




Definition at line 134 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LP1\_\-REG@{LP1\_\-REG}}
\index{LP1\_\-REG@{LP1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LP1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LP1\_\-REG~LINIDR}\label{ATmega32M1_8h_5db9a98acea93e260829e616c8fb6828}




Definition at line 135 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LPERR\_\-REG@{LPERR\_\-REG}}
\index{LPERR\_\-REG@{LPERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LPERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LPERR\_\-REG~LINERR}\label{ATmega32M1_8h_5d443eec3cef641b50eaa7dd2d4baa13}




Definition at line 608 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LRXDL0\_\-REG@{LRXDL0\_\-REG}}
\index{LRXDL0\_\-REG@{LRXDL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LRXDL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LRXDL0\_\-REG~LINDLR}\label{ATmega32M1_8h_8899ced7dc80108a9a817098b49817c1}




Definition at line 960 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LRXDL1\_\-REG@{LRXDL1\_\-REG}}
\index{LRXDL1\_\-REG@{LRXDL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LRXDL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LRXDL1\_\-REG~LINDLR}\label{ATmega32M1_8h_9a88458f8309a4357c2a789113066a49}




Definition at line 961 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LRXDL2\_\-REG@{LRXDL2\_\-REG}}
\index{LRXDL2\_\-REG@{LRXDL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LRXDL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LRXDL2\_\-REG~LINDLR}\label{ATmega32M1_8h_6234db4f366273d361c5a52b69d042c6}




Definition at line 962 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LRXDL3\_\-REG@{LRXDL3\_\-REG}}
\index{LRXDL3\_\-REG@{LRXDL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LRXDL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LRXDL3\_\-REG~LINDLR}\label{ATmega32M1_8h_b5af40505bcb15cc0109eb904cc245fb}




Definition at line 963 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LRXOK\_\-REG@{LRXOK\_\-REG}}
\index{LRXOK\_\-REG@{LRXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LRXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LRXOK\_\-REG~LINSIR}\label{ATmega32M1_8h_217702ec726f460a596db08fc381a7f3}




Definition at line 1008 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LSERR\_\-REG@{LSERR\_\-REG}}
\index{LSERR\_\-REG@{LSERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LSERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LSERR\_\-REG~LINERR}\label{ATmega32M1_8h_2fed2f1b70eea1c0383c0c52f630a422}




Definition at line 609 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LSWRES\_\-REG@{LSWRES\_\-REG}}
\index{LSWRES\_\-REG@{LSWRES\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LSWRES\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LSWRES\_\-REG~LINCR}\label{ATmega32M1_8h_e9ea61ca391dc92318964344611425b2}




Definition at line 187 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LTOERR\_\-REG@{LTOERR\_\-REG}}
\index{LTOERR\_\-REG@{LTOERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LTOERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LTOERR\_\-REG~LINERR}\label{ATmega32M1_8h_a16f94b5f84c38ee5ac6af3613ec90bd}




Definition at line 612 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LTXDL0\_\-REG@{LTXDL0\_\-REG}}
\index{LTXDL0\_\-REG@{LTXDL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LTXDL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LTXDL0\_\-REG~LINDLR}\label{ATmega32M1_8h_13e638ca72bf580faf20a7b61b9bb34d}




Definition at line 964 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LTXDL1\_\-REG@{LTXDL1\_\-REG}}
\index{LTXDL1\_\-REG@{LTXDL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LTXDL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LTXDL1\_\-REG~LINDLR}\label{ATmega32M1_8h_c3850137bc59ccb41cb9342676ab9232}




Definition at line 965 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LTXDL2\_\-REG@{LTXDL2\_\-REG}}
\index{LTXDL2\_\-REG@{LTXDL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LTXDL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LTXDL2\_\-REG~LINDLR}\label{ATmega32M1_8h_b3bf3871ca3ef6460671b62300e5ef33}




Definition at line 966 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LTXDL3\_\-REG@{LTXDL3\_\-REG}}
\index{LTXDL3\_\-REG@{LTXDL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LTXDL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LTXDL3\_\-REG~LINDLR}\label{ATmega32M1_8h_4f43837b6beb8bb708f6cd7bb33df616}




Definition at line 967 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!LTXOK\_\-REG@{LTXOK\_\-REG}}
\index{LTXOK\_\-REG@{LTXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[LTXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define LTXOK\_\-REG~LINSIR}\label{ATmega32M1_8h_1138ee1c8006ea32e0dcc674983edb39}




Definition at line 1009 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MISO\_\-A\_\-BIT@{MISO\_\-A\_\-BIT}}
\index{MISO\_\-A\_\-BIT@{MISO\_\-A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MISO\_\-A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define MISO\_\-A\_\-BIT~2}\label{ATmega32M1_8h_0aee50afdb6b7f8efaa5d4961d357f85}




Definition at line 1481 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MISO\_\-A\_\-PORT@{MISO\_\-A\_\-PORT}}
\index{MISO\_\-A\_\-PORT@{MISO\_\-A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MISO\_\-A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define MISO\_\-A\_\-PORT~PORTD}\label{ATmega32M1_8h_9d8e8bf255a046af92a27430654e3d17}




Definition at line 1480 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MISO\_\-BIT@{MISO\_\-BIT}}
\index{MISO\_\-BIT@{MISO\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MISO\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define MISO\_\-BIT~0}\label{ATmega32M1_8h_143c27a1d9cba360256a7ebc9dcd2733}




Definition at line 1341 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MISO\_\-PORT@{MISO\_\-PORT}}
\index{MISO\_\-PORT@{MISO\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MISO\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define MISO\_\-PORT~PORTB}\label{ATmega32M1_8h_95f821d043691db6725895729e274a56}




Definition at line 1340 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOBNB0\_\-REG@{MOBNB0\_\-REG}}
\index{MOBNB0\_\-REG@{MOBNB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOBNB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MOBNB0\_\-REG~CANPAGE}\label{ATmega32M1_8h_c88b5c0914a3a7687141305d7defd4cd}




Definition at line 362 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOBNB1\_\-REG@{MOBNB1\_\-REG}}
\index{MOBNB1\_\-REG@{MOBNB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOBNB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MOBNB1\_\-REG~CANPAGE}\label{ATmega32M1_8h_4455ffc7600ff51ef43372cb4651b608}




Definition at line 363 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOBNB2\_\-REG@{MOBNB2\_\-REG}}
\index{MOBNB2\_\-REG@{MOBNB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOBNB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MOBNB2\_\-REG~CANPAGE}\label{ATmega32M1_8h_ebc0b0d6c2be7a3dd7ef239608c3f150}




Definition at line 364 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOBNB3\_\-REG@{MOBNB3\_\-REG}}
\index{MOBNB3\_\-REG@{MOBNB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOBNB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MOBNB3\_\-REG~CANPAGE}\label{ATmega32M1_8h_42a3c62dcebd0386ada51c279d8ebc5a}




Definition at line 365 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOSI\_\-A\_\-BIT@{MOSI\_\-A\_\-BIT}}
\index{MOSI\_\-A\_\-BIT@{MOSI\_\-A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOSI\_\-A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define MOSI\_\-A\_\-BIT~3}\label{ATmega32M1_8h_65821f0eaf41e342b7d5c349e1b5c367}




Definition at line 1494 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOSI\_\-A\_\-PORT@{MOSI\_\-A\_\-PORT}}
\index{MOSI\_\-A\_\-PORT@{MOSI\_\-A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOSI\_\-A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define MOSI\_\-A\_\-PORT~PORTD}\label{ATmega32M1_8h_a800d26e6654d9aeefc881b27d1ba71d}




Definition at line 1493 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOSI\_\-BIT@{MOSI\_\-BIT}}
\index{MOSI\_\-BIT@{MOSI\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOSI\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define MOSI\_\-BIT~1}\label{ATmega32M1_8h_a0a9f8c47b5f9ba838a069c79f406966}




Definition at line 1348 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MOSI\_\-PORT@{MOSI\_\-PORT}}
\index{MOSI\_\-PORT@{MOSI\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MOSI\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define MOSI\_\-PORT~PORTB}\label{ATmega32M1_8h_f2f6be3b3791ee39c85aae843889eba4}




Definition at line 1347 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MSTR\_\-REG@{MSTR\_\-REG}}
\index{MSTR\_\-REG@{MSTR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MSTR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MSTR\_\-REG~SPCR}\label{ATmega32M1_8h_703198bb1a73ec980c5616b3e42fd8e1}




Definition at line 715 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MUX0\_\-REG@{MUX0\_\-REG}}
\index{MUX0\_\-REG@{MUX0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MUX0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MUX0\_\-REG~ADMUX}\label{ATmega32M1_8h_ad7153866c349c19882e6c4ad03dc967}




Definition at line 256 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MUX1\_\-REG@{MUX1\_\-REG}}
\index{MUX1\_\-REG@{MUX1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MUX1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MUX1\_\-REG~ADMUX}\label{ATmega32M1_8h_c92509a04e802dc37f1a9d74d2d91acf}




Definition at line 257 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MUX2\_\-REG@{MUX2\_\-REG}}
\index{MUX2\_\-REG@{MUX2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MUX2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MUX2\_\-REG~ADMUX}\label{ATmega32M1_8h_b83108254bd47fda37d0788b4c8dd1fd}




Definition at line 258 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MUX3\_\-REG@{MUX3\_\-REG}}
\index{MUX3\_\-REG@{MUX3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MUX3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MUX3\_\-REG~ADMUX}\label{ATmega32M1_8h_f137d4cf4a3ef0e748d21b86b09d1fd8}




Definition at line 259 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!MUX4\_\-REG@{MUX4\_\-REG}}
\index{MUX4\_\-REG@{MUX4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[MUX4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define MUX4\_\-REG~ADMUX}\label{ATmega32M1_8h_05864f3e90f7e93cdd1a383dc94e8c71}




Definition at line 260 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!N\_\-REG@{N\_\-REG}}
\index{N\_\-REG@{N\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[N\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define N\_\-REG~SREG}\label{ATmega32M1_8h_22560b62179eb57d9a1f102291689234}




Definition at line 910 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC0A\_\-BIT@{OC0A\_\-BIT}}
\index{OC0A\_\-BIT@{OC0A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC0A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC0A\_\-BIT~3}\label{ATmega32M1_8h_0ad390da135913247403e8652024f03d}




Definition at line 1490 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC0A\_\-PORT@{OC0A\_\-PORT}}
\index{OC0A\_\-PORT@{OC0A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC0A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC0A\_\-PORT~PORTD}\label{ATmega32M1_8h_8709b42aa8a925818f664ef4b2cc0ac9}




Definition at line 1489 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC0B\_\-BIT@{OC0B\_\-BIT}}
\index{OC0B\_\-BIT@{OC0B\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC0B\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC0B\_\-BIT~1}\label{ATmega32M1_8h_21274478f5f4bad3636de29945a2be9d}




Definition at line 1540 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC0B\_\-PORT@{OC0B\_\-PORT}}
\index{OC0B\_\-PORT@{OC0B\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC0B\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC0B\_\-PORT~PORTE}\label{ATmega32M1_8h_5224aff8eb24cefcb135075432349b26}




Definition at line 1539 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC1A\_\-BIT@{OC1A\_\-BIT}}
\index{OC1A\_\-BIT@{OC1A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC1A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC1A\_\-BIT~2}\label{ATmega32M1_8h_b10bebfafd55626ab8c0c10ffd9eb980}




Definition at line 1479 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC1A\_\-PORT@{OC1A\_\-PORT}}
\index{OC1A\_\-PORT@{OC1A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC1A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC1A\_\-PORT~PORTD}\label{ATmega32M1_8h_ad77395bba354e9e8438c5695dd715f0}




Definition at line 1478 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC1B\_\-BIT@{OC1B\_\-BIT}}
\index{OC1B\_\-BIT@{OC1B\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC1B\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC1B\_\-BIT~1}\label{ATmega32M1_8h_6eb7f16661c66ca74e9a789bd3ed4603}




Definition at line 1410 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OC1B\_\-PORT@{OC1B\_\-PORT}}
\index{OC1B\_\-PORT@{OC1B\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OC1B\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define OC1B\_\-PORT~PORTC}\label{ATmega32M1_8h_4bf8c482d9b6b46f157cf0f0ee23d231}




Definition at line 1409 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCD\_\-BIT@{OCD\_\-BIT}}
\index{OCD\_\-BIT@{OCD\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCD\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define OCD\_\-BIT~0}\label{ATmega32M1_8h_582104d1c4cf76531a5c8e62c9849b2f}




Definition at line 1535 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCD\_\-PORT@{OCD\_\-PORT}}
\index{OCD\_\-PORT@{OCD\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCD\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define OCD\_\-PORT~PORTE}\label{ATmega32M1_8h_e3eeb5071a9a9b40b7145bb389fec962}




Definition at line 1534 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCF0A\_\-REG@{OCF0A\_\-REG}}
\index{OCF0A\_\-REG@{OCF0A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCF0A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCF0A\_\-REG~TIFR0}\label{ATmega32M1_8h_3f48357e922f77b8fd07213ee72f6569}




Definition at line 1330 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCF0B\_\-REG@{OCF0B\_\-REG}}
\index{OCF0B\_\-REG@{OCF0B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCF0B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCF0B\_\-REG~TIFR0}\label{ATmega32M1_8h_f5f73cadcda2b3b40e99b59ac99e27a6}




Definition at line 1331 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCF1A\_\-REG@{OCF1A\_\-REG}}
\index{OCF1A\_\-REG@{OCF1A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCF1A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCF1A\_\-REG~TIFR1}\label{ATmega32M1_8h_e5a9fd43ec78b0c6e7539d83dd7926d0}




Definition at line 722 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCF1B\_\-REG@{OCF1B\_\-REG}}
\index{OCF1B\_\-REG@{OCF1B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCF1B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCF1B\_\-REG~TIFR1}\label{ATmega32M1_8h_19204424f02b6bc01cd85668a8253653}




Definition at line 723 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCIE0A\_\-REG@{OCIE0A\_\-REG}}
\index{OCIE0A\_\-REG@{OCIE0A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCIE0A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCIE0A\_\-REG~TIMSK0}\label{ATmega32M1_8h_b5623e5597e7929772a52ce8a5e35294}




Definition at line 1201 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCIE0B\_\-REG@{OCIE0B\_\-REG}}
\index{OCIE0B\_\-REG@{OCIE0B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCIE0B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCIE0B\_\-REG~TIMSK0}\label{ATmega32M1_8h_04c1067deee0b48f3d9e21fcaa364107}




Definition at line 1202 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCIE1A\_\-REG@{OCIE1A\_\-REG}}
\index{OCIE1A\_\-REG@{OCIE1A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCIE1A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCIE1A\_\-REG~TIMSK1}\label{ATmega32M1_8h_6854b762f72186a69a1dd3f894dba314}




Definition at line 1206 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCIE1B\_\-REG@{OCIE1B\_\-REG}}
\index{OCIE1B\_\-REG@{OCIE1B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCIE1B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCIE1B\_\-REG~TIMSK1}\label{ATmega32M1_8h_3e8f094902415901534c310eda7676b6}




Definition at line 1207 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH0\_\-REG@{OCR1AH0\_\-REG}}
\index{OCR1AH0\_\-REG@{OCR1AH0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH0\_\-REG~OCR1AH}\label{ATmega32M1_8h_76cffc78592a8684b6ad766495c67b97}




Definition at line 1309 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH1\_\-REG@{OCR1AH1\_\-REG}}
\index{OCR1AH1\_\-REG@{OCR1AH1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH1\_\-REG~OCR1AH}\label{ATmega32M1_8h_6ff71710a669c3a301f09038c2656ffc}




Definition at line 1310 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH2\_\-REG@{OCR1AH2\_\-REG}}
\index{OCR1AH2\_\-REG@{OCR1AH2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH2\_\-REG~OCR1AH}\label{ATmega32M1_8h_664d0221d7d1b04e8de8a7c0a570d72a}




Definition at line 1311 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH3\_\-REG@{OCR1AH3\_\-REG}}
\index{OCR1AH3\_\-REG@{OCR1AH3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH3\_\-REG~OCR1AH}\label{ATmega32M1_8h_9ae7117bbdff1b73881565ffa935d23c}




Definition at line 1312 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH4\_\-REG@{OCR1AH4\_\-REG}}
\index{OCR1AH4\_\-REG@{OCR1AH4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH4\_\-REG~OCR1AH}\label{ATmega32M1_8h_8b9575a62855f2b00b42c86d2b8fe219}




Definition at line 1313 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH5\_\-REG@{OCR1AH5\_\-REG}}
\index{OCR1AH5\_\-REG@{OCR1AH5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH5\_\-REG~OCR1AH}\label{ATmega32M1_8h_86de588f6310ed6535f319930d6b8769}




Definition at line 1314 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH6\_\-REG@{OCR1AH6\_\-REG}}
\index{OCR1AH6\_\-REG@{OCR1AH6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH6\_\-REG~OCR1AH}\label{ATmega32M1_8h_de644871a6cf22e4afa55e62d129c76d}




Definition at line 1315 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AH7\_\-REG@{OCR1AH7\_\-REG}}
\index{OCR1AH7\_\-REG@{OCR1AH7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AH7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AH7\_\-REG~OCR1AH}\label{ATmega32M1_8h_9175672c5137d382cb7caf6f420dcb95}




Definition at line 1316 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL0\_\-REG@{OCR1AL0\_\-REG}}
\index{OCR1AL0\_\-REG@{OCR1AL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL0\_\-REG~OCR1AL}\label{ATmega32M1_8h_b7156a04d6b271949b7089575b073e77}




Definition at line 1319 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL1\_\-REG@{OCR1AL1\_\-REG}}
\index{OCR1AL1\_\-REG@{OCR1AL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL1\_\-REG~OCR1AL}\label{ATmega32M1_8h_804cba0f39f492d7288da3e1f6493b10}




Definition at line 1320 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL2\_\-REG@{OCR1AL2\_\-REG}}
\index{OCR1AL2\_\-REG@{OCR1AL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL2\_\-REG~OCR1AL}\label{ATmega32M1_8h_602b5d751df6f8a1ce0f5884c8b2d5bf}




Definition at line 1321 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL3\_\-REG@{OCR1AL3\_\-REG}}
\index{OCR1AL3\_\-REG@{OCR1AL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL3\_\-REG~OCR1AL}\label{ATmega32M1_8h_c9878f7beec4913a6b24ec1e7508808b}




Definition at line 1322 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL4\_\-REG@{OCR1AL4\_\-REG}}
\index{OCR1AL4\_\-REG@{OCR1AL4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL4\_\-REG~OCR1AL}\label{ATmega32M1_8h_9be063575a85da6c6db243a5b6ac5206}




Definition at line 1323 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL5\_\-REG@{OCR1AL5\_\-REG}}
\index{OCR1AL5\_\-REG@{OCR1AL5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL5\_\-REG~OCR1AL}\label{ATmega32M1_8h_e36d5d702dbe5b043976c0000b45ae68}




Definition at line 1324 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL6\_\-REG@{OCR1AL6\_\-REG}}
\index{OCR1AL6\_\-REG@{OCR1AL6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL6\_\-REG~OCR1AL}\label{ATmega32M1_8h_9f0194a166ce44212f4d6440922e59c9}




Definition at line 1325 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1AL7\_\-REG@{OCR1AL7\_\-REG}}
\index{OCR1AL7\_\-REG@{OCR1AL7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1AL7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1AL7\_\-REG~OCR1AL}\label{ATmega32M1_8h_0de9246b2f818d409d6993151145fc2a}




Definition at line 1326 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH0\_\-REG@{OCR1BH0\_\-REG}}
\index{OCR1BH0\_\-REG@{OCR1BH0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH0\_\-REG~OCR1BH}\label{ATmega32M1_8h_90791a27ce9aa3fcea198f2ec16cfa64}




Definition at line 831 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH1\_\-REG@{OCR1BH1\_\-REG}}
\index{OCR1BH1\_\-REG@{OCR1BH1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH1\_\-REG~OCR1BH}\label{ATmega32M1_8h_9e03ced9340990fe7ecd3423dae31980}




Definition at line 832 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH2\_\-REG@{OCR1BH2\_\-REG}}
\index{OCR1BH2\_\-REG@{OCR1BH2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH2\_\-REG~OCR1BH}\label{ATmega32M1_8h_6ac61e2e86fc965f95f7644738e61eca}




Definition at line 833 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH3\_\-REG@{OCR1BH3\_\-REG}}
\index{OCR1BH3\_\-REG@{OCR1BH3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH3\_\-REG~OCR1BH}\label{ATmega32M1_8h_55ad741d2c801dc9017fa2c2ad823d2a}




Definition at line 834 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH4\_\-REG@{OCR1BH4\_\-REG}}
\index{OCR1BH4\_\-REG@{OCR1BH4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH4\_\-REG~OCR1BH}\label{ATmega32M1_8h_8930d72ff1f6f17838f77a46a49b7a79}




Definition at line 835 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH5\_\-REG@{OCR1BH5\_\-REG}}
\index{OCR1BH5\_\-REG@{OCR1BH5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH5\_\-REG~OCR1BH}\label{ATmega32M1_8h_56b20d68d95b42a236d43ddf4dcd1347}




Definition at line 836 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH6\_\-REG@{OCR1BH6\_\-REG}}
\index{OCR1BH6\_\-REG@{OCR1BH6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH6\_\-REG~OCR1BH}\label{ATmega32M1_8h_ed6a5892547bd6b908c7f9928d3af230}




Definition at line 837 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BH7\_\-REG@{OCR1BH7\_\-REG}}
\index{OCR1BH7\_\-REG@{OCR1BH7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BH7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BH7\_\-REG~OCR1BH}\label{ATmega32M1_8h_45247e9966bc2f27f882f06bf698fe1c}




Definition at line 838 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL0\_\-REG@{OCR1BL0\_\-REG}}
\index{OCR1BL0\_\-REG@{OCR1BL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL0\_\-REG~OCR1BL}\label{ATmega32M1_8h_6ad4667f6c5c346e18da3e0c00b6bbc1}




Definition at line 821 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL1\_\-REG@{OCR1BL1\_\-REG}}
\index{OCR1BL1\_\-REG@{OCR1BL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL1\_\-REG~OCR1BL}\label{ATmega32M1_8h_4274b00fe5273b7ea53619bd50482c1c}




Definition at line 822 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL2\_\-REG@{OCR1BL2\_\-REG}}
\index{OCR1BL2\_\-REG@{OCR1BL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL2\_\-REG~OCR1BL}\label{ATmega32M1_8h_02f1190659700630c6df9ab5097f389b}




Definition at line 823 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL3\_\-REG@{OCR1BL3\_\-REG}}
\index{OCR1BL3\_\-REG@{OCR1BL3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL3\_\-REG~OCR1BL}\label{ATmega32M1_8h_6b78c083255a72d7d27a2e0c7914b2dc}




Definition at line 824 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL4\_\-REG@{OCR1BL4\_\-REG}}
\index{OCR1BL4\_\-REG@{OCR1BL4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL4\_\-REG~OCR1BL}\label{ATmega32M1_8h_73a707d5eb50faa3982813f045b41bfe}




Definition at line 825 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL5\_\-REG@{OCR1BL5\_\-REG}}
\index{OCR1BL5\_\-REG@{OCR1BL5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL5\_\-REG~OCR1BL}\label{ATmega32M1_8h_be97392680683ca730835f616bf2fc32}




Definition at line 826 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL6\_\-REG@{OCR1BL6\_\-REG}}
\index{OCR1BL6\_\-REG@{OCR1BL6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL6\_\-REG~OCR1BL}\label{ATmega32M1_8h_df48e8bc5fc4ec622c28b7b32a50bbae}




Definition at line 827 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OCR1BL7\_\-REG@{OCR1BL7\_\-REG}}
\index{OCR1BL7\_\-REG@{OCR1BL7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OCR1BL7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OCR1BL7\_\-REG~OCR1BL}\label{ATmega32M1_8h_69b15121693bfb5afe29134091766be3}




Definition at line 828 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OVFG\_\-REG@{OVFG\_\-REG}}
\index{OVFG\_\-REG@{OVFG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OVFG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OVFG\_\-REG~CANGSTA}\label{ATmega32M1_8h_7ec13412b7ba62f44ece7faccd55af8a}




Definition at line 291 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OVRQ\_\-REG@{OVRQ\_\-REG}}
\index{OVRQ\_\-REG@{OVRQ\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OVRQ\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OVRQ\_\-REG~CANGCON}\label{ATmega32M1_8h_fb550949051c8a3fbbfc32463bf55b19}




Definition at line 300 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!OVRTIM\_\-REG@{OVRTIM\_\-REG}}
\index{OVRTIM\_\-REG@{OVRTIM\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[OVRTIM\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define OVRTIM\_\-REG~CANGIT}\label{ATmega32M1_8h_b328f22020a2fcbee8b2e412787a68ac}




Definition at line 592 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PAOC0\_\-REG@{PAOC0\_\-REG}}
\index{PAOC0\_\-REG@{PAOC0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PAOC0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PAOC0\_\-REG~PMIC0}\label{ATmega32M1_8h_e5fdeaf9d934e40caaf1db4d3b2a1b94}




Definition at line 1106 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PAOC1\_\-REG@{PAOC1\_\-REG}}
\index{PAOC1\_\-REG@{PAOC1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PAOC1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PAOC1\_\-REG~PMIC1}\label{ATmega32M1_8h_d34d26f3116246e52e663b807386009a}




Definition at line 524 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PAOC2\_\-REG@{PAOC2\_\-REG}}
\index{PAOC2\_\-REG@{PAOC2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PAOC2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PAOC2\_\-REG~PMIC2}\label{ATmega32M1_8h_25e861db8ceb793c52e06769d532fede}




Definition at line 510 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCCYC\_\-REG@{PCCYC\_\-REG}}
\index{PCCYC\_\-REG@{PCCYC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCCYC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCCYC\_\-REG~PCTL}\label{ATmega32M1_8h_f416878b296d8782f6dfd561406d6c49}




Definition at line 551 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIE0\_\-REG@{PCIE0\_\-REG}}
\index{PCIE0\_\-REG@{PCIE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIE0\_\-REG~PCICR}\label{ATmega32M1_8h_cc36a3d829c10e1ba4aa71009041b1f1}




Definition at line 616 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIE1\_\-REG@{PCIE1\_\-REG}}
\index{PCIE1\_\-REG@{PCIE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIE1\_\-REG~PCICR}\label{ATmega32M1_8h_fd57d01796fa506dea12b2cda35765ee}




Definition at line 617 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIE2\_\-REG@{PCIE2\_\-REG}}
\index{PCIE2\_\-REG@{PCIE2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIE2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIE2\_\-REG~PCICR}\label{ATmega32M1_8h_5dbfc71688e23360406fc27b02d95d85}




Definition at line 618 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIE3\_\-REG@{PCIE3\_\-REG}}
\index{PCIE3\_\-REG@{PCIE3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIE3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIE3\_\-REG~PCICR}\label{ATmega32M1_8h_a5a92d156fcf32e925f3cdef968bee51}




Definition at line 619 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIF0\_\-REG@{PCIF0\_\-REG}}
\index{PCIF0\_\-REG@{PCIF0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIF0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIF0\_\-REG~PCIFR}\label{ATmega32M1_8h_84ad580ef98d182b06ddfe9266c1ea93}




Definition at line 892 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIF1\_\-REG@{PCIF1\_\-REG}}
\index{PCIF1\_\-REG@{PCIF1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIF1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIF1\_\-REG~PCIFR}\label{ATmega32M1_8h_600943af3d98c3c7ba13ac0f6e2fe6ce}




Definition at line 893 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIF2\_\-REG@{PCIF2\_\-REG}}
\index{PCIF2\_\-REG@{PCIF2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIF2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIF2\_\-REG~PCIFR}\label{ATmega32M1_8h_bd21ba20d8df6518b1b38519760db34a}




Definition at line 894 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCIF3\_\-REG@{PCIF3\_\-REG}}
\index{PCIF3\_\-REG@{PCIF3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCIF3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCIF3\_\-REG~PCIFR}\label{ATmega32M1_8h_b5bccf5ec8d0a7c9e8f2aacd4318ff03}




Definition at line 895 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT0\_\-BIT@{PCINT0\_\-BIT}}
\index{PCINT0\_\-BIT@{PCINT0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT0\_\-BIT~0}\label{ATmega32M1_8h_6343b0a3cda1861529245574df547615}




Definition at line 1345 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT0\_\-PORT@{PCINT0\_\-PORT}}
\index{PCINT0\_\-PORT@{PCINT0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT0\_\-PORT~PORTB}\label{ATmega32M1_8h_b1de4465aa9d7a044fff09cd97ef13a6}




Definition at line 1344 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT0\_\-REG@{PCINT0\_\-REG}}
\index{PCINT0\_\-REG@{PCINT0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT0\_\-REG~PCMSK0}\label{ATmega32M1_8h_1fc8de5bdf89aa2195c98f52d21f7ba1}




Definition at line 1229 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT10\_\-BIT@{PCINT10\_\-BIT}}
\index{PCINT10\_\-BIT@{PCINT10\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT10\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT10\_\-BIT~2}\label{ATmega32M1_8h_0a73af10fa857337d63feff8567a2880}




Definition at line 1421 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT10\_\-PORT@{PCINT10\_\-PORT}}
\index{PCINT10\_\-PORT@{PCINT10\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT10\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT10\_\-PORT~PORTC}\label{ATmega32M1_8h_255681d931b2685b01a842d2772e41dc}




Definition at line 1420 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT10\_\-REG@{PCINT10\_\-REG}}
\index{PCINT10\_\-REG@{PCINT10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT10\_\-REG~PCMSK1}\label{ATmega32M1_8h_9e49252fb3f8c92bfaf3814031cc919f}




Definition at line 1241 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT11\_\-BIT@{PCINT11\_\-BIT}}
\index{PCINT11\_\-BIT@{PCINT11\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT11\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT11\_\-BIT~3}\label{ATmega32M1_8h_c84fb45b3701f222d1b0ccb32afc0821}




Definition at line 1430 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT11\_\-PORT@{PCINT11\_\-PORT}}
\index{PCINT11\_\-PORT@{PCINT11\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT11\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT11\_\-PORT~PORTC}\label{ATmega32M1_8h_ad00eea33f59e9f7bf3f62eb0a8ee289}




Definition at line 1429 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT11\_\-REG@{PCINT11\_\-REG}}
\index{PCINT11\_\-REG@{PCINT11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT11\_\-REG~PCMSK1}\label{ATmega32M1_8h_fcbb1e0e89a9e5a26cccf46dafaf3fd8}




Definition at line 1242 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT12\_\-BIT@{PCINT12\_\-BIT}}
\index{PCINT12\_\-BIT@{PCINT12\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT12\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT12\_\-BIT~4}\label{ATmega32M1_8h_9295f935895b92e56d558bcda39f40fb}




Definition at line 1439 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT12\_\-PORT@{PCINT12\_\-PORT}}
\index{PCINT12\_\-PORT@{PCINT12\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT12\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT12\_\-PORT~PORTC}\label{ATmega32M1_8h_04b0a08cf28d3c3e7f8cfc422b933718}




Definition at line 1438 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT12\_\-REG@{PCINT12\_\-REG}}
\index{PCINT12\_\-REG@{PCINT12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT12\_\-REG~PCMSK1}\label{ATmega32M1_8h_29aa9a90bda96d18e17809b76a53ce91}




Definition at line 1243 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT13\_\-BIT@{PCINT13\_\-BIT}}
\index{PCINT13\_\-BIT@{PCINT13\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT13\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT13\_\-BIT~5}\label{ATmega32M1_8h_a90caf5b501df32853960ab522a622a2}




Definition at line 1448 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT13\_\-PORT@{PCINT13\_\-PORT}}
\index{PCINT13\_\-PORT@{PCINT13\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT13\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT13\_\-PORT~PORTC}\label{ATmega32M1_8h_72b8e0cd92b6e206bce9b2a30e5adbf9}




Definition at line 1447 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT13\_\-REG@{PCINT13\_\-REG}}
\index{PCINT13\_\-REG@{PCINT13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT13\_\-REG~PCMSK1}\label{ATmega32M1_8h_ebf531a77c3a584910f781592d70dc02}




Definition at line 1244 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT14\_\-BIT@{PCINT14\_\-BIT}}
\index{PCINT14\_\-BIT@{PCINT14\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT14\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT14\_\-BIT~6}\label{ATmega32M1_8h_20800c19dfed6d6009e47fd102d954e8}




Definition at line 1455 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT14\_\-PORT@{PCINT14\_\-PORT}}
\index{PCINT14\_\-PORT@{PCINT14\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT14\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT14\_\-PORT~PORTC}\label{ATmega32M1_8h_6b14a9bb14e86341079f8b9687581088}




Definition at line 1454 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT14\_\-REG@{PCINT14\_\-REG}}
\index{PCINT14\_\-REG@{PCINT14\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT14\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT14\_\-REG~PCMSK1}\label{ATmega32M1_8h_f2e7bf7f3dc1971468e01e03c1f520de}




Definition at line 1245 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT15\_\-BIT@{PCINT15\_\-BIT}}
\index{PCINT15\_\-BIT@{PCINT15\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT15\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT15\_\-BIT~7}\label{ATmega32M1_8h_9e0b6363cf5fa860edca1a9d676abf33}




Definition at line 1462 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT15\_\-PORT@{PCINT15\_\-PORT}}
\index{PCINT15\_\-PORT@{PCINT15\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT15\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT15\_\-PORT~PORTC}\label{ATmega32M1_8h_3f140ca45181c62dc09d56065bfe1014}




Definition at line 1461 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT15\_\-REG@{PCINT15\_\-REG}}
\index{PCINT15\_\-REG@{PCINT15\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT15\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT15\_\-REG~PCMSK1}\label{ATmega32M1_8h_dda3fd70fb83520df2b5ce893f28b5e1}




Definition at line 1246 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT16\_\-BIT@{PCINT16\_\-BIT}}
\index{PCINT16\_\-BIT@{PCINT16\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT16\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT16\_\-BIT~0}\label{ATmega32M1_8h_3217f2d1231d72476bbb157a75a8b7aa}




Definition at line 1467 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT16\_\-PORT@{PCINT16\_\-PORT}}
\index{PCINT16\_\-PORT@{PCINT16\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT16\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT16\_\-PORT~PORTD}\label{ATmega32M1_8h_b7a6b9b5f2789218843ac0e1f2a67bca}




Definition at line 1466 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT16\_\-REG@{PCINT16\_\-REG}}
\index{PCINT16\_\-REG@{PCINT16\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT16\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT16\_\-REG~PCMSK2}\label{ATmega32M1_8h_bf0ab3ce0ac40f0ac82797f6b810a7d0}




Definition at line 1249 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT17\_\-BIT@{PCINT17\_\-BIT}}
\index{PCINT17\_\-BIT@{PCINT17\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT17\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT17\_\-BIT~1}\label{ATmega32M1_8h_4575346f39e89c7029b938ae9c9e90c7}




Definition at line 1474 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT17\_\-PORT@{PCINT17\_\-PORT}}
\index{PCINT17\_\-PORT@{PCINT17\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT17\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT17\_\-PORT~PORTD}\label{ATmega32M1_8h_bc3e802a8d92bb258bcc733814e053f4}




Definition at line 1473 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT17\_\-REG@{PCINT17\_\-REG}}
\index{PCINT17\_\-REG@{PCINT17\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT17\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT17\_\-REG~PCMSK2}\label{ATmega32M1_8h_c8a3b57e777baaf415cd80f7d9f10b64}




Definition at line 1250 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT18\_\-BIT@{PCINT18\_\-BIT}}
\index{PCINT18\_\-BIT@{PCINT18\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT18\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT18\_\-BIT~2}\label{ATmega32M1_8h_504e12b0f89ecd2842737cb14a7a2bc9}




Definition at line 1483 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT18\_\-PORT@{PCINT18\_\-PORT}}
\index{PCINT18\_\-PORT@{PCINT18\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT18\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT18\_\-PORT~PORTD}\label{ATmega32M1_8h_bd044a43b028eb8586b369161aeb9fd0}




Definition at line 1482 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT18\_\-REG@{PCINT18\_\-REG}}
\index{PCINT18\_\-REG@{PCINT18\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT18\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT18\_\-REG~PCMSK2}\label{ATmega32M1_8h_e0e3e841abbce7b46e0547dd138c9876}




Definition at line 1251 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT19\_\-BIT@{PCINT19\_\-BIT}}
\index{PCINT19\_\-BIT@{PCINT19\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT19\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT19\_\-BIT~3}\label{ATmega32M1_8h_a0eae51b82d7c68189193fb5c2f619d3}




Definition at line 1496 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT19\_\-PORT@{PCINT19\_\-PORT}}
\index{PCINT19\_\-PORT@{PCINT19\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT19\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT19\_\-PORT~PORTD}\label{ATmega32M1_8h_b49a63634328e81f4599ebd656b15f5e}




Definition at line 1495 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT19\_\-REG@{PCINT19\_\-REG}}
\index{PCINT19\_\-REG@{PCINT19\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT19\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT19\_\-REG~PCMSK2}\label{ATmega32M1_8h_9c4b816479bd9727f8ab5d24e341394d}




Definition at line 1252 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT1\_\-BIT@{PCINT1\_\-BIT}}
\index{PCINT1\_\-BIT@{PCINT1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT1\_\-BIT~1}\label{ATmega32M1_8h_21ec77de7608babe865d1919de82464b}




Definition at line 1352 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT1\_\-PORT@{PCINT1\_\-PORT}}
\index{PCINT1\_\-PORT@{PCINT1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT1\_\-PORT~PORTB}\label{ATmega32M1_8h_8c69086f27273ba63e5a57c547d976f2}




Definition at line 1351 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT1\_\-REG@{PCINT1\_\-REG}}
\index{PCINT1\_\-REG@{PCINT1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT1\_\-REG~PCMSK0}\label{ATmega32M1_8h_26779181002e7ea2d1b1671cde829992}




Definition at line 1230 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT20\_\-BIT@{PCINT20\_\-BIT}}
\index{PCINT20\_\-BIT@{PCINT20\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT20\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT20\_\-BIT~4}\label{ATmega32M1_8h_2f9341fe18d49942f6858e641aa3dd7f}




Definition at line 1509 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT20\_\-PORT@{PCINT20\_\-PORT}}
\index{PCINT20\_\-PORT@{PCINT20\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT20\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT20\_\-PORT~PORTD}\label{ATmega32M1_8h_74858f30c5300c9dce3e12ebd92a6fa1}




Definition at line 1508 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT20\_\-REG@{PCINT20\_\-REG}}
\index{PCINT20\_\-REG@{PCINT20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT20\_\-REG~PCMSK2}\label{ATmega32M1_8h_c8c892a6c5587fd50a130f89cb14b61b}




Definition at line 1253 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT21\_\-BIT@{PCINT21\_\-BIT}}
\index{PCINT21\_\-BIT@{PCINT21\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT21\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT21\_\-BIT~5}\label{ATmega32M1_8h_ccb5685d337030d8a5ffa2cdf73b64ab}




Definition at line 1516 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT21\_\-PORT@{PCINT21\_\-PORT}}
\index{PCINT21\_\-PORT@{PCINT21\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT21\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT21\_\-PORT~PORTD}\label{ATmega32M1_8h_0137b6c2acd9d76ce4586748118cc565}




Definition at line 1515 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT21\_\-REG@{PCINT21\_\-REG}}
\index{PCINT21\_\-REG@{PCINT21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT21\_\-REG~PCMSK2}\label{ATmega32M1_8h_4422978f27fe5b8581fea2273acecd31}




Definition at line 1254 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT22\_\-BIT@{PCINT22\_\-BIT}}
\index{PCINT22\_\-BIT@{PCINT22\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT22\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT22\_\-BIT~6}\label{ATmega32M1_8h_8ef2532b34c5a2696638e1658ce122fd}




Definition at line 1525 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT22\_\-PORT@{PCINT22\_\-PORT}}
\index{PCINT22\_\-PORT@{PCINT22\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT22\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT22\_\-PORT~PORTD}\label{ATmega32M1_8h_156540cd455de4328b41ded7fa75addc}




Definition at line 1524 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT22\_\-REG@{PCINT22\_\-REG}}
\index{PCINT22\_\-REG@{PCINT22\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT22\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT22\_\-REG~PCMSK2}\label{ATmega32M1_8h_51d40b10cc8126a7ee9164bd8b64ca53}




Definition at line 1255 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT23\_\-BIT@{PCINT23\_\-BIT}}
\index{PCINT23\_\-BIT@{PCINT23\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT23\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT23\_\-BIT~7}\label{ATmega32M1_8h_caffa5c9526cdb91611b98d3790a76c4}




Definition at line 1530 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT23\_\-PORT@{PCINT23\_\-PORT}}
\index{PCINT23\_\-PORT@{PCINT23\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT23\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT23\_\-PORT~PORTD}\label{ATmega32M1_8h_69705360f01e4340d9c8664f3146eff1}




Definition at line 1529 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT23\_\-REG@{PCINT23\_\-REG}}
\index{PCINT23\_\-REG@{PCINT23\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT23\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT23\_\-REG~PCMSK2}\label{ATmega32M1_8h_8ec6161ee9c110f699617e9cb45e9802}




Definition at line 1256 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT24\_\-BIT@{PCINT24\_\-BIT}}
\index{PCINT24\_\-BIT@{PCINT24\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT24\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT24\_\-BIT~0}\label{ATmega32M1_8h_852f598f5a0dd510009f3d4f03ddecaf}




Definition at line 1537 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT24\_\-PORT@{PCINT24\_\-PORT}}
\index{PCINT24\_\-PORT@{PCINT24\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT24\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT24\_\-PORT~PORTE}\label{ATmega32M1_8h_ccc9a52aa334f02bca2c27700f5ae6ea}




Definition at line 1536 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT24\_\-REG@{PCINT24\_\-REG}}
\index{PCINT24\_\-REG@{PCINT24\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT24\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT24\_\-REG~PCMSK3}\label{ATmega32M1_8h_dd0662f3b05fa41169a4e7be36711806}




Definition at line 1259 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT25\_\-BIT@{PCINT25\_\-BIT}}
\index{PCINT25\_\-BIT@{PCINT25\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT25\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT25\_\-BIT~1}\label{ATmega32M1_8h_c68299745cbbff15657047f79758e79e}




Definition at line 1544 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT25\_\-PORT@{PCINT25\_\-PORT}}
\index{PCINT25\_\-PORT@{PCINT25\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT25\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT25\_\-PORT~PORTE}\label{ATmega32M1_8h_10825ccd90a7c98cfe0697135c1ffe0c}




Definition at line 1543 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT25\_\-REG@{PCINT25\_\-REG}}
\index{PCINT25\_\-REG@{PCINT25\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT25\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT25\_\-REG~PCMSK3}\label{ATmega32M1_8h_6af1c61ff3e53e5fb2cca1781a50e946}




Definition at line 1260 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT26\_\-BIT@{PCINT26\_\-BIT}}
\index{PCINT26\_\-BIT@{PCINT26\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT26\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT26\_\-BIT~2}\label{ATmega32M1_8h_c4d0625d8fc235c171bc88ea1cf5ab8d}




Definition at line 1551 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT26\_\-PORT@{PCINT26\_\-PORT}}
\index{PCINT26\_\-PORT@{PCINT26\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT26\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT26\_\-PORT~PORTE}\label{ATmega32M1_8h_b56f8edd84f4de7c5ef4a7c1a686f43d}




Definition at line 1550 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT26\_\-REG@{PCINT26\_\-REG}}
\index{PCINT26\_\-REG@{PCINT26\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT26\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT26\_\-REG~PCMSK3}\label{ATmega32M1_8h_cf232d5e08e92725332b3941ff104d6c}




Definition at line 1261 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT2\_\-BIT@{PCINT2\_\-BIT}}
\index{PCINT2\_\-BIT@{PCINT2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT2\_\-BIT~2}\label{ATmega32M1_8h_2b66add4059fd601c26fe3294c796523}




Definition at line 1361 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT2\_\-PORT@{PCINT2\_\-PORT}}
\index{PCINT2\_\-PORT@{PCINT2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT2\_\-PORT~PORTB}\label{ATmega32M1_8h_10edcff04cefc04d6fed3a93defa81cd}




Definition at line 1360 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT2\_\-REG@{PCINT2\_\-REG}}
\index{PCINT2\_\-REG@{PCINT2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT2\_\-REG~PCMSK0}\label{ATmega32M1_8h_44afccf44b76d9f61fa5bab7738f7e99}




Definition at line 1231 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT3\_\-BIT@{PCINT3\_\-BIT}}
\index{PCINT3\_\-BIT@{PCINT3\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT3\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT3\_\-BIT~3}\label{ATmega32M1_8h_396bf5081b19670b6359887a3a444d01}




Definition at line 1366 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT3\_\-PORT@{PCINT3\_\-PORT}}
\index{PCINT3\_\-PORT@{PCINT3\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT3\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT3\_\-PORT~PORTB}\label{ATmega32M1_8h_ddbb79db12851a8f87875e653550eab2}




Definition at line 1365 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT3\_\-REG@{PCINT3\_\-REG}}
\index{PCINT3\_\-REG@{PCINT3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT3\_\-REG~PCMSK0}\label{ATmega32M1_8h_ad92aed06b38cc34ccb0e3aac10ab4fa}




Definition at line 1232 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT4\_\-BIT@{PCINT4\_\-BIT}}
\index{PCINT4\_\-BIT@{PCINT4\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT4\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT4\_\-BIT~4}\label{ATmega32M1_8h_bb9ad6e6592b88daee39ab22ce9c527e}




Definition at line 1371 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT4\_\-PORT@{PCINT4\_\-PORT}}
\index{PCINT4\_\-PORT@{PCINT4\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT4\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT4\_\-PORT~PORTB}\label{ATmega32M1_8h_a1251765304df676b79d1c30413bf8e8}




Definition at line 1370 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT4\_\-REG@{PCINT4\_\-REG}}
\index{PCINT4\_\-REG@{PCINT4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT4\_\-REG~PCMSK0}\label{ATmega32M1_8h_493d06113c3fbb3742899a614534ae01}




Definition at line 1233 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT5\_\-BIT@{PCINT5\_\-BIT}}
\index{PCINT5\_\-BIT@{PCINT5\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT5\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT5\_\-BIT~5}\label{ATmega32M1_8h_204ad527a04b554131e812fab2871026}




Definition at line 1382 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT5\_\-PORT@{PCINT5\_\-PORT}}
\index{PCINT5\_\-PORT@{PCINT5\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT5\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT5\_\-PORT~PORTB}\label{ATmega32M1_8h_d1ad035a0efaa1ef9f67d6a5c359c80f}




Definition at line 1381 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT5\_\-REG@{PCINT5\_\-REG}}
\index{PCINT5\_\-REG@{PCINT5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT5\_\-REG~PCMSK0}\label{ATmega32M1_8h_c297aacfe6169d64a6bf5ab747518b14}




Definition at line 1234 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT6\_\-BIT@{PCINT6\_\-BIT}}
\index{PCINT6\_\-BIT@{PCINT6\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT6\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT6\_\-BIT~6}\label{ATmega32M1_8h_a9de0b658c86105fd69c302e77326ad8}




Definition at line 1389 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT6\_\-PORT@{PCINT6\_\-PORT}}
\index{PCINT6\_\-PORT@{PCINT6\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT6\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT6\_\-PORT~PORTB}\label{ATmega32M1_8h_86962228dadea234942d02d9c225d0db}




Definition at line 1388 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT6\_\-REG@{PCINT6\_\-REG}}
\index{PCINT6\_\-REG@{PCINT6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT6\_\-REG~PCMSK0}\label{ATmega32M1_8h_1bc3b580d9f16a4a296d306edd493175}




Definition at line 1235 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT7\_\-BIT@{PCINT7\_\-BIT}}
\index{PCINT7\_\-BIT@{PCINT7\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT7\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT7\_\-BIT~7}\label{ATmega32M1_8h_6dc4e799e523eec1e4f7656e25c4990d}




Definition at line 1398 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT7\_\-PORT@{PCINT7\_\-PORT}}
\index{PCINT7\_\-PORT@{PCINT7\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT7\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT7\_\-PORT~PORTB}\label{ATmega32M1_8h_fd0a2ab6a4540e83edc2c5b0e643eb48}




Definition at line 1397 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT7\_\-REG@{PCINT7\_\-REG}}
\index{PCINT7\_\-REG@{PCINT7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT7\_\-REG~PCMSK0}\label{ATmega32M1_8h_328583e3ab557eaaf35c0d1d28c57356}




Definition at line 1236 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT8\_\-BIT@{PCINT8\_\-BIT}}
\index{PCINT8\_\-BIT@{PCINT8\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT8\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT8\_\-BIT~0}\label{ATmega32M1_8h_8d797cc448266b873f1be177195f5ea7}




Definition at line 1405 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT8\_\-PORT@{PCINT8\_\-PORT}}
\index{PCINT8\_\-PORT@{PCINT8\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT8\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT8\_\-PORT~PORTC}\label{ATmega32M1_8h_ce2e7eeb5f08ed840ecc4039eb257878}




Definition at line 1404 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT8\_\-REG@{PCINT8\_\-REG}}
\index{PCINT8\_\-REG@{PCINT8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT8\_\-REG~PCMSK1}\label{ATmega32M1_8h_14d972f3e5b6be4d07dd2ae24aef01ec}




Definition at line 1239 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT9\_\-BIT@{PCINT9\_\-BIT}}
\index{PCINT9\_\-BIT@{PCINT9\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT9\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT9\_\-BIT~1}\label{ATmega32M1_8h_4cdd3ace79b4689fc5f632fe351aa819}




Definition at line 1414 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT9\_\-PORT@{PCINT9\_\-PORT}}
\index{PCINT9\_\-PORT@{PCINT9\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT9\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT9\_\-PORT~PORTC}\label{ATmega32M1_8h_827ff9585812b881142a51eb14919455}




Definition at line 1413 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCINT9\_\-REG@{PCINT9\_\-REG}}
\index{PCINT9\_\-REG@{PCINT9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCINT9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCINT9\_\-REG~PCMSK1}\label{ATmega32M1_8h_36ba853a00599ea9182d2e51c9da91ae}




Definition at line 1240 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PCLKSEL\_\-REG@{PCLKSEL\_\-REG}}
\index{PCLKSEL\_\-REG@{PCLKSEL\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PCLKSEL\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PCLKSEL\_\-REG~PCTL}\label{ATmega32M1_8h_e0ea18393a805a7c77e53c7eaaeaf691}




Definition at line 552 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PELEV0\_\-REG@{PELEV0\_\-REG}}
\index{PELEV0\_\-REG@{PELEV0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PELEV0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PELEV0\_\-REG~PMIC0}\label{ATmega32M1_8h_eb48873d329cdd0a2d6d0a6eaced98e2}




Definition at line 1108 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PELEV1\_\-REG@{PELEV1\_\-REG}}
\index{PELEV1\_\-REG@{PELEV1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PELEV1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PELEV1\_\-REG~PMIC1}\label{ATmega32M1_8h_67bf8b80ffea44197d0a453871e2ba80}




Definition at line 526 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PELEV2\_\-REG@{PELEV2\_\-REG}}
\index{PELEV2\_\-REG@{PELEV2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PELEV2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PELEV2\_\-REG~PMIC2}\label{ATmega32M1_8h_ea784dfb2b0cb814ffa067cc83f33027}




Definition at line 512 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEOP\_\-REG@{PEOP\_\-REG}}
\index{PEOP\_\-REG@{PEOP\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEOP\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEOP\_\-REG~PIFR}\label{ATmega32M1_8h_a15d1fd8cbad1539d05e77ceba7dd2bf}




Definition at line 1002 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEOPE\_\-REG@{PEOPE\_\-REG}}
\index{PEOPE\_\-REG@{PEOPE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEOPE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEOPE\_\-REG~PIM}\label{ATmega32M1_8h_5acd4a17af30031b14c206bceedf5884}




Definition at line 190 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEV0\_\-REG@{PEV0\_\-REG}}
\index{PEV0\_\-REG@{PEV0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEV0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEV0\_\-REG~PIFR}\label{ATmega32M1_8h_2a9ec853782402678e42b4c1db4a662b}




Definition at line 1003 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEV1\_\-REG@{PEV1\_\-REG}}
\index{PEV1\_\-REG@{PEV1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEV1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEV1\_\-REG~PIFR}\label{ATmega32M1_8h_86527bae2e7c8c3921ab158ba27348d1}




Definition at line 1004 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEV2\_\-REG@{PEV2\_\-REG}}
\index{PEV2\_\-REG@{PEV2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEV2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEV2\_\-REG~PIFR}\label{ATmega32M1_8h_0770c780ee4b194862ded28fda5ba75a}




Definition at line 1005 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEVE0\_\-REG@{PEVE0\_\-REG}}
\index{PEVE0\_\-REG@{PEVE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEVE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEVE0\_\-REG~PIM}\label{ATmega32M1_8h_5ec48bd4c020d437650abca9cfc41475}




Definition at line 191 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEVE1\_\-REG@{PEVE1\_\-REG}}
\index{PEVE1\_\-REG@{PEVE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEVE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEVE1\_\-REG~PIM}\label{ATmega32M1_8h_b3f0a596b091c7d4839939d6b9aa8618}




Definition at line 192 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PEVE2\_\-REG@{PEVE2\_\-REG}}
\index{PEVE2\_\-REG@{PEVE2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PEVE2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PEVE2\_\-REG~PIM}\label{ATmega32M1_8h_d262436268f2238cf4d9135e1c4cabcf}




Definition at line 193 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PFLTE0\_\-REG@{PFLTE0\_\-REG}}
\index{PFLTE0\_\-REG@{PFLTE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PFLTE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PFLTE0\_\-REG~PMIC0}\label{ATmega32M1_8h_2340b91c520584d9829d586a95e44559}




Definition at line 1107 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PFLTE1\_\-REG@{PFLTE1\_\-REG}}
\index{PFLTE1\_\-REG@{PFLTE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PFLTE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PFLTE1\_\-REG~PMIC1}\label{ATmega32M1_8h_2cfd7e0939f1ef040b112d3cd8490442}




Definition at line 525 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PFLTE2\_\-REG@{PFLTE2\_\-REG}}
\index{PFLTE2\_\-REG@{PFLTE2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PFLTE2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PFLTE2\_\-REG~PMIC2}\label{ATmega32M1_8h_74bd20dfd96637bbd76edc1fa05156ae}




Definition at line 511 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PGERS\_\-REG@{PGERS\_\-REG}}
\index{PGERS\_\-REG@{PGERS\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PGERS\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PGERS\_\-REG~SPMCSR}\label{ATmega32M1_8h_82d438bd58be8d9b45211cc6b0448c80}




Definition at line 1131 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PGWRT\_\-REG@{PGWRT\_\-REG}}
\index{PGWRT\_\-REG@{PGWRT\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PGWRT\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PGWRT\_\-REG~SPMCSR}\label{ATmega32M1_8h_baa71acc8944bcb1f49f429b64858848}




Definition at line 1132 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PHS10\_\-REG@{PHS10\_\-REG}}
\index{PHS10\_\-REG@{PHS10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PHS10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PHS10\_\-REG~CANBT3}\label{ATmega32M1_8h_d30e2c8a90b4dd80c31fcebde14ad311}




Definition at line 1154 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PHS11\_\-REG@{PHS11\_\-REG}}
\index{PHS11\_\-REG@{PHS11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PHS11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PHS11\_\-REG~CANBT3}\label{ATmega32M1_8h_c29bf5fc9c61645514ed79a2af9ca7cf}




Definition at line 1155 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PHS12\_\-REG@{PHS12\_\-REG}}
\index{PHS12\_\-REG@{PHS12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PHS12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PHS12\_\-REG~CANBT3}\label{ATmega32M1_8h_3e70ef0ca54578b36d1655b84043fc4a}




Definition at line 1156 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PHS20\_\-REG@{PHS20\_\-REG}}
\index{PHS20\_\-REG@{PHS20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PHS20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PHS20\_\-REG~CANBT3}\label{ATmega32M1_8h_9851a408f32b4ffb97df289a11673920}




Definition at line 1157 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PHS21\_\-REG@{PHS21\_\-REG}}
\index{PHS21\_\-REG@{PHS21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PHS21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PHS21\_\-REG~CANBT3}\label{ATmega32M1_8h_000f8b30884bc045154b9bdb2ce788c0}




Definition at line 1158 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PHS22\_\-REG@{PHS22\_\-REG}}
\index{PHS22\_\-REG@{PHS22\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PHS22\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PHS22\_\-REG~CANBT3}\label{ATmega32M1_8h_d8778370f84c19dfbf2f916768eb4a21}




Definition at line 1159 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB0\_\-REG@{PINB0\_\-REG}}
\index{PINB0\_\-REG@{PINB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB0\_\-REG~PINB}\label{ATmega32M1_8h_887fe46ced810578885cd2f9576233fb}




Definition at line 1274 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB1\_\-REG@{PINB1\_\-REG}}
\index{PINB1\_\-REG@{PINB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB1\_\-REG~PINB}\label{ATmega32M1_8h_96950156307fa8076767279ccb521a6d}




Definition at line 1275 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB2\_\-REG@{PINB2\_\-REG}}
\index{PINB2\_\-REG@{PINB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB2\_\-REG~PINB}\label{ATmega32M1_8h_d5bd17b842b338d4383087c675a3a4f3}




Definition at line 1276 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB3\_\-REG@{PINB3\_\-REG}}
\index{PINB3\_\-REG@{PINB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB3\_\-REG~PINB}\label{ATmega32M1_8h_f127a9d3187d4d3886ec120fa904d239}




Definition at line 1277 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB4\_\-REG@{PINB4\_\-REG}}
\index{PINB4\_\-REG@{PINB4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB4\_\-REG~PINB}\label{ATmega32M1_8h_33bd7788e70872f9c27adc27fd324222}




Definition at line 1278 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB5\_\-REG@{PINB5\_\-REG}}
\index{PINB5\_\-REG@{PINB5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB5\_\-REG~PINB}\label{ATmega32M1_8h_18e2c7ec2497f5b8511ef2ddf50c457f}




Definition at line 1279 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB6\_\-REG@{PINB6\_\-REG}}
\index{PINB6\_\-REG@{PINB6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB6\_\-REG~PINB}\label{ATmega32M1_8h_8f1d15c22912ea93248edbdb38c57613}




Definition at line 1280 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINB7\_\-REG@{PINB7\_\-REG}}
\index{PINB7\_\-REG@{PINB7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINB7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINB7\_\-REG~PINB}\label{ATmega32M1_8h_1d86f584aa520ed5ccb77ce75c9eae18}




Definition at line 1281 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC0\_\-REG@{PINC0\_\-REG}}
\index{PINC0\_\-REG@{PINC0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC0\_\-REG~PINC}\label{ATmega32M1_8h_984887ac1306ffad8619864dbe4aeb6c}




Definition at line 1264 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC1\_\-REG@{PINC1\_\-REG}}
\index{PINC1\_\-REG@{PINC1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC1\_\-REG~PINC}\label{ATmega32M1_8h_82a27fb661bad0dec12bde59dddb2727}




Definition at line 1265 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC2\_\-REG@{PINC2\_\-REG}}
\index{PINC2\_\-REG@{PINC2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC2\_\-REG~PINC}\label{ATmega32M1_8h_78d3466ea7b6947862a9e17470c3066c}




Definition at line 1266 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC3\_\-REG@{PINC3\_\-REG}}
\index{PINC3\_\-REG@{PINC3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC3\_\-REG~PINC}\label{ATmega32M1_8h_eaeffa85d587275a0e7aee361cfbf565}




Definition at line 1267 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC4\_\-REG@{PINC4\_\-REG}}
\index{PINC4\_\-REG@{PINC4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC4\_\-REG~PINC}\label{ATmega32M1_8h_e192a1c5a73087e8a3e4e3fc9206cbbf}




Definition at line 1268 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC5\_\-REG@{PINC5\_\-REG}}
\index{PINC5\_\-REG@{PINC5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC5\_\-REG~PINC}\label{ATmega32M1_8h_e2a9e6c7635d45c09c344ceba4682b0a}




Definition at line 1269 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC6\_\-REG@{PINC6\_\-REG}}
\index{PINC6\_\-REG@{PINC6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC6\_\-REG~PINC}\label{ATmega32M1_8h_a81df41ca11e7ebea79c80ae0c949f0a}




Definition at line 1270 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINC7\_\-REG@{PINC7\_\-REG}}
\index{PINC7\_\-REG@{PINC7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINC7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINC7\_\-REG~PINC}\label{ATmega32M1_8h_02c0d913157f5c1c513e7eac592b9f02}




Definition at line 1271 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND0\_\-REG@{PIND0\_\-REG}}
\index{PIND0\_\-REG@{PIND0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND0\_\-REG~PIND}\label{ATmega32M1_8h_a609777bfcce6a82df13bce5f936098d}




Definition at line 1299 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND1\_\-REG@{PIND1\_\-REG}}
\index{PIND1\_\-REG@{PIND1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND1\_\-REG~PIND}\label{ATmega32M1_8h_1ad1507c23c6cf423b3025d4a39562d3}




Definition at line 1300 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND2\_\-REG@{PIND2\_\-REG}}
\index{PIND2\_\-REG@{PIND2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND2\_\-REG~PIND}\label{ATmega32M1_8h_1b5c29ef4f69103a73acd4f0447750c7}




Definition at line 1301 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND3\_\-REG@{PIND3\_\-REG}}
\index{PIND3\_\-REG@{PIND3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND3\_\-REG~PIND}\label{ATmega32M1_8h_7d2631f802b2ca028f29cf8cbc4ffaea}




Definition at line 1302 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND4\_\-REG@{PIND4\_\-REG}}
\index{PIND4\_\-REG@{PIND4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND4\_\-REG~PIND}\label{ATmega32M1_8h_9e6b29bab09914583be1a5e87f3424dd}




Definition at line 1303 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND5\_\-REG@{PIND5\_\-REG}}
\index{PIND5\_\-REG@{PIND5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND5\_\-REG~PIND}\label{ATmega32M1_8h_d1dae0888e0366064adc5ed0cf0dcebe}




Definition at line 1304 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND6\_\-REG@{PIND6\_\-REG}}
\index{PIND6\_\-REG@{PIND6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND6\_\-REG~PIND}\label{ATmega32M1_8h_f519b4a06c9e3b294ddfe66f184cf5c0}




Definition at line 1305 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PIND7\_\-REG@{PIND7\_\-REG}}
\index{PIND7\_\-REG@{PIND7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PIND7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PIND7\_\-REG~PIND}\label{ATmega32M1_8h_7fcabd03860b96146470667f8c50bcde}




Definition at line 1306 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINE0\_\-REG@{PINE0\_\-REG}}
\index{PINE0\_\-REG@{PINE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINE0\_\-REG~PINE}\label{ATmega32M1_8h_6b213b01ac85ec6dac7d172c98fc07e5}




Definition at line 1294 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINE1\_\-REG@{PINE1\_\-REG}}
\index{PINE1\_\-REG@{PINE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINE1\_\-REG~PINE}\label{ATmega32M1_8h_bc83897e895f2704ca1fe151e9dc6232}




Definition at line 1295 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PINE2\_\-REG@{PINE2\_\-REG}}
\index{PINE2\_\-REG@{PINE2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PINE2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PINE2\_\-REG~PINE}\label{ATmega32M1_8h_0dd398265eb338f8bdba20a037095003}




Definition at line 1296 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PISEL0\_\-REG@{PISEL0\_\-REG}}
\index{PISEL0\_\-REG@{PISEL0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PISEL0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PISEL0\_\-REG~PMIC0}\label{ATmega32M1_8h_12807d75f2c5c1c5e3247845722ecb28}




Definition at line 1109 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PISEL1\_\-REG@{PISEL1\_\-REG}}
\index{PISEL1\_\-REG@{PISEL1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PISEL1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PISEL1\_\-REG~PMIC1}\label{ATmega32M1_8h_158b80413e073fed09adabeca7d6da2f}




Definition at line 527 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PISEL2\_\-REG@{PISEL2\_\-REG}}
\index{PISEL2\_\-REG@{PISEL2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PISEL2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PISEL2\_\-REG~PMIC2}\label{ATmega32M1_8h_6d93c9eacc036e587d8f3f6e9d91eb1c}




Definition at line 513 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PLLE\_\-REG@{PLLE\_\-REG}}
\index{PLLE\_\-REG@{PLLE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PLLE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PLLE\_\-REG~PLLCSR}\label{ATmega32M1_8h_2b4e023627fda8f9cb907c3a125fdeb3}




Definition at line 882 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PLLF\_\-REG@{PLLF\_\-REG}}
\index{PLLF\_\-REG@{PLLF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PLLF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PLLF\_\-REG~PLLCSR}\label{ATmega32M1_8h_fccebddf2b784e0c0feab4cb8cf07b23}




Definition at line 883 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PLOCK\_\-REG@{PLOCK\_\-REG}}
\index{PLOCK\_\-REG@{PLOCK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PLOCK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PLOCK\_\-REG~PLLCSR}\label{ATmega32M1_8h_67d2f6fc90e520d71102300ab0776602}




Definition at line 881 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PMODE\_\-REG@{PMODE\_\-REG}}
\index{PMODE\_\-REG@{PMODE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PMODE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PMODE\_\-REG~PCNF}\label{ATmega32M1_8h_93a46639f86107adfe172ec77aeb194e}




Definition at line 1142 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-00\_\-REG@{POCR0RA\_\-00\_\-REG}}
\index{POCR0RA\_\-00\_\-REG@{POCR0RA\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-00\_\-REG~POCR0RAH}\label{ATmega32M1_8h_16614ad9df12527a817aefd8409e7056}




Definition at line 678 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-01\_\-REG@{POCR0RA\_\-01\_\-REG}}
\index{POCR0RA\_\-01\_\-REG@{POCR0RA\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-01\_\-REG~POCR0RAH}\label{ATmega32M1_8h_170a1fa1ea3f3a848c9ca6a03f946da7}




Definition at line 679 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-0\_\-REG@{POCR0RA\_\-0\_\-REG}}
\index{POCR0RA\_\-0\_\-REG@{POCR0RA\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-0\_\-REG~POCR0RAL}\label{ATmega32M1_8h_91785c42183e7d081a7c2b4ecd4b4a8c}




Definition at line 650 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-1\_\-REG@{POCR0RA\_\-1\_\-REG}}
\index{POCR0RA\_\-1\_\-REG@{POCR0RA\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-1\_\-REG~POCR0RAL}\label{ATmega32M1_8h_f2b7f8b26a194bc8f68e0d208a041b1e}




Definition at line 651 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-2\_\-REG@{POCR0RA\_\-2\_\-REG}}
\index{POCR0RA\_\-2\_\-REG@{POCR0RA\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-2\_\-REG~POCR0RAL}\label{ATmega32M1_8h_4add6761a48d88edbc4daf799b1f0119}




Definition at line 652 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-3\_\-REG@{POCR0RA\_\-3\_\-REG}}
\index{POCR0RA\_\-3\_\-REG@{POCR0RA\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-3\_\-REG~POCR0RAL}\label{ATmega32M1_8h_b5188e469b9072265aba4812bdb87e03}




Definition at line 653 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-4\_\-REG@{POCR0RA\_\-4\_\-REG}}
\index{POCR0RA\_\-4\_\-REG@{POCR0RA\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-4\_\-REG~POCR0RAL}\label{ATmega32M1_8h_3a1913fec4dec566f16975f3a9f496e7}




Definition at line 654 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-5\_\-REG@{POCR0RA\_\-5\_\-REG}}
\index{POCR0RA\_\-5\_\-REG@{POCR0RA\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-5\_\-REG~POCR0RAL}\label{ATmega32M1_8h_e8574672bc27e2a8a588dc5db5fd9bb9}




Definition at line 655 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-6\_\-REG@{POCR0RA\_\-6\_\-REG}}
\index{POCR0RA\_\-6\_\-REG@{POCR0RA\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-6\_\-REG~POCR0RAL}\label{ATmega32M1_8h_37b3ed3cb74de5ac7ff485393fd76744}




Definition at line 656 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-7\_\-REG@{POCR0RA\_\-7\_\-REG}}
\index{POCR0RA\_\-7\_\-REG@{POCR0RA\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-7\_\-REG~POCR0RAL}\label{ATmega32M1_8h_efaf73b87573e84f6e50fad55785277b}




Definition at line 657 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-8\_\-REG@{POCR0RA\_\-8\_\-REG}}
\index{POCR0RA\_\-8\_\-REG@{POCR0RA\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-8\_\-REG~POCR0RAH}\label{ATmega32M1_8h_e4fa7d2c5e679a5f75f8fd9bab11e01a}




Definition at line 676 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0RA\_\-9\_\-REG@{POCR0RA\_\-9\_\-REG}}
\index{POCR0RA\_\-9\_\-REG@{POCR0RA\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0RA\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0RA\_\-9\_\-REG~POCR0RAH}\label{ATmega32M1_8h_ba1df4311295454f41c38cfc8e82f882}




Definition at line 677 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-00\_\-REG@{POCR0SA\_\-00\_\-REG}}
\index{POCR0SA\_\-00\_\-REG@{POCR0SA\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-00\_\-REG~POCR0SAH}\label{ATmega32M1_8h_2656124040fb488c37146cbe36d0e23c}




Definition at line 930 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-01\_\-REG@{POCR0SA\_\-01\_\-REG}}
\index{POCR0SA\_\-01\_\-REG@{POCR0SA\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-01\_\-REG~POCR0SAH}\label{ATmega32M1_8h_299ca4caa126b7aa756b223b17251db4}




Definition at line 931 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-0\_\-REG@{POCR0SA\_\-0\_\-REG}}
\index{POCR0SA\_\-0\_\-REG@{POCR0SA\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-0\_\-REG~POCR0SAL}\label{ATmega32M1_8h_ec0eb60a971fa698096347d65ef110e4}




Definition at line 944 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-1\_\-REG@{POCR0SA\_\-1\_\-REG}}
\index{POCR0SA\_\-1\_\-REG@{POCR0SA\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-1\_\-REG~POCR0SAL}\label{ATmega32M1_8h_4ef2f7bfea6ce2968dea73529f353d53}




Definition at line 945 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-2\_\-REG@{POCR0SA\_\-2\_\-REG}}
\index{POCR0SA\_\-2\_\-REG@{POCR0SA\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-2\_\-REG~POCR0SAL}\label{ATmega32M1_8h_933889d81dde87b18a850d81f1a4c09d}




Definition at line 946 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-3\_\-REG@{POCR0SA\_\-3\_\-REG}}
\index{POCR0SA\_\-3\_\-REG@{POCR0SA\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-3\_\-REG~POCR0SAL}\label{ATmega32M1_8h_d9d75ae2d37b8c1b958d1b0d66b0d4ff}




Definition at line 947 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-4\_\-REG@{POCR0SA\_\-4\_\-REG}}
\index{POCR0SA\_\-4\_\-REG@{POCR0SA\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-4\_\-REG~POCR0SAL}\label{ATmega32M1_8h_22494a8c4df099187eb534fb81e7d92e}




Definition at line 948 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-5\_\-REG@{POCR0SA\_\-5\_\-REG}}
\index{POCR0SA\_\-5\_\-REG@{POCR0SA\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-5\_\-REG~POCR0SAL}\label{ATmega32M1_8h_765d3999253a498b09693bda80644bee}




Definition at line 949 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-6\_\-REG@{POCR0SA\_\-6\_\-REG}}
\index{POCR0SA\_\-6\_\-REG@{POCR0SA\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-6\_\-REG~POCR0SAL}\label{ATmega32M1_8h_d5b845e46200f632ebb1dacfa5837fb2}




Definition at line 950 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-7\_\-REG@{POCR0SA\_\-7\_\-REG}}
\index{POCR0SA\_\-7\_\-REG@{POCR0SA\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-7\_\-REG~POCR0SAL}\label{ATmega32M1_8h_f4d2b3ebd7f2cbb40e72fff2412d2974}




Definition at line 951 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-8\_\-REG@{POCR0SA\_\-8\_\-REG}}
\index{POCR0SA\_\-8\_\-REG@{POCR0SA\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-8\_\-REG~POCR0SAH}\label{ATmega32M1_8h_fc1be647c0e16c9657093dd3614e8c42}




Definition at line 928 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SA\_\-9\_\-REG@{POCR0SA\_\-9\_\-REG}}
\index{POCR0SA\_\-9\_\-REG@{POCR0SA\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SA\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SA\_\-9\_\-REG~POCR0SAH}\label{ATmega32M1_8h_47272789ed10c1eb4fca46f16c6da36e}




Definition at line 929 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-00\_\-REG@{POCR0SB\_\-00\_\-REG}}
\index{POCR0SB\_\-00\_\-REG@{POCR0SB\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-00\_\-REG~POCR0SBH}\label{ATmega32M1_8h_3e472b3e8bbfcd2587e98fd037002665}




Definition at line 1336 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-01\_\-REG@{POCR0SB\_\-01\_\-REG}}
\index{POCR0SB\_\-01\_\-REG@{POCR0SB\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-01\_\-REG~POCR0SBH}\label{ATmega32M1_8h_76652f384b382c45f1e970537d9b4cd6}




Definition at line 1337 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-0\_\-REG@{POCR0SB\_\-0\_\-REG}}
\index{POCR0SB\_\-0\_\-REG@{POCR0SB\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-0\_\-REG~POCR0SBL}\label{ATmega32M1_8h_82f2523a13b8f3a14c92eae7f73e0415}




Definition at line 1073 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-1\_\-REG@{POCR0SB\_\-1\_\-REG}}
\index{POCR0SB\_\-1\_\-REG@{POCR0SB\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-1\_\-REG~POCR0SBL}\label{ATmega32M1_8h_17fae918bee71c97d649553b2c68405a}




Definition at line 1074 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-2\_\-REG@{POCR0SB\_\-2\_\-REG}}
\index{POCR0SB\_\-2\_\-REG@{POCR0SB\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-2\_\-REG~POCR0SBL}\label{ATmega32M1_8h_67d44c1c063b51b40cad65e72584e929}




Definition at line 1075 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-3\_\-REG@{POCR0SB\_\-3\_\-REG}}
\index{POCR0SB\_\-3\_\-REG@{POCR0SB\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-3\_\-REG~POCR0SBL}\label{ATmega32M1_8h_cb28dad753296df39cbd6512dc2b603f}




Definition at line 1076 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-4\_\-REG@{POCR0SB\_\-4\_\-REG}}
\index{POCR0SB\_\-4\_\-REG@{POCR0SB\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-4\_\-REG~POCR0SBL}\label{ATmega32M1_8h_43b06bd2cf45e8f954b5c6058b927a61}




Definition at line 1077 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-5\_\-REG@{POCR0SB\_\-5\_\-REG}}
\index{POCR0SB\_\-5\_\-REG@{POCR0SB\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-5\_\-REG~POCR0SBL}\label{ATmega32M1_8h_b333669530d319dd6e3db1071bd3010b}




Definition at line 1078 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-6\_\-REG@{POCR0SB\_\-6\_\-REG}}
\index{POCR0SB\_\-6\_\-REG@{POCR0SB\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-6\_\-REG~POCR0SBL}\label{ATmega32M1_8h_f7f777480bc77faebcc933796879f3bc}




Definition at line 1079 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-7\_\-REG@{POCR0SB\_\-7\_\-REG}}
\index{POCR0SB\_\-7\_\-REG@{POCR0SB\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-7\_\-REG~POCR0SBL}\label{ATmega32M1_8h_6c0779ab4403c97fa97b693eb8929a43}




Definition at line 1080 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-8\_\-REG@{POCR0SB\_\-8\_\-REG}}
\index{POCR0SB\_\-8\_\-REG@{POCR0SB\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-8\_\-REG~POCR0SBH}\label{ATmega32M1_8h_73815796eb80a854ba74f6c6300eb5be}




Definition at line 1334 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR0SB\_\-9\_\-REG@{POCR0SB\_\-9\_\-REG}}
\index{POCR0SB\_\-9\_\-REG@{POCR0SB\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR0SB\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR0SB\_\-9\_\-REG~POCR0SBH}\label{ATmega32M1_8h_b0d907037b3841ab96b664e1122a4b8f}




Definition at line 1335 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-00\_\-REG@{POCR1RA\_\-00\_\-REG}}
\index{POCR1RA\_\-00\_\-REG@{POCR1RA\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-00\_\-REG~POCR1RAH}\label{ATmega32M1_8h_3aa5fc4c8d78967463697515b34ccef7}




Definition at line 140 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-01\_\-REG@{POCR1RA\_\-01\_\-REG}}
\index{POCR1RA\_\-01\_\-REG@{POCR1RA\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-01\_\-REG~POCR1RAH}\label{ATmega32M1_8h_c90b025290f98ab2f4111b17b82ddf78}




Definition at line 141 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-0\_\-REG@{POCR1RA\_\-0\_\-REG}}
\index{POCR1RA\_\-0\_\-REG@{POCR1RA\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-0\_\-REG~POCR1RAL}\label{ATmega32M1_8h_12b076bda3d65cace5cc7fb4f4aa16ba}




Definition at line 118 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-1\_\-REG@{POCR1RA\_\-1\_\-REG}}
\index{POCR1RA\_\-1\_\-REG@{POCR1RA\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-1\_\-REG~POCR1RAL}\label{ATmega32M1_8h_76858b4c16bce82fee72532d56c27936}




Definition at line 119 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-2\_\-REG@{POCR1RA\_\-2\_\-REG}}
\index{POCR1RA\_\-2\_\-REG@{POCR1RA\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-2\_\-REG~POCR1RAL}\label{ATmega32M1_8h_441b290fc87a054a1c9e37f350787114}




Definition at line 120 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-3\_\-REG@{POCR1RA\_\-3\_\-REG}}
\index{POCR1RA\_\-3\_\-REG@{POCR1RA\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-3\_\-REG~POCR1RAL}\label{ATmega32M1_8h_981d36520ab128447c83d53eeaac03cb}




Definition at line 121 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-4\_\-REG@{POCR1RA\_\-4\_\-REG}}
\index{POCR1RA\_\-4\_\-REG@{POCR1RA\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-4\_\-REG~POCR1RAL}\label{ATmega32M1_8h_b49eaf5ac256f7ef12d2a4ee8dc4d78f}




Definition at line 122 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-5\_\-REG@{POCR1RA\_\-5\_\-REG}}
\index{POCR1RA\_\-5\_\-REG@{POCR1RA\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-5\_\-REG~POCR1RAL}\label{ATmega32M1_8h_f1adb65ea3bbfb6c34525b901b8e433e}




Definition at line 123 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-6\_\-REG@{POCR1RA\_\-6\_\-REG}}
\index{POCR1RA\_\-6\_\-REG@{POCR1RA\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-6\_\-REG~POCR1RAL}\label{ATmega32M1_8h_352bb8388b9e0d4620204334bbfdf152}




Definition at line 124 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-7\_\-REG@{POCR1RA\_\-7\_\-REG}}
\index{POCR1RA\_\-7\_\-REG@{POCR1RA\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-7\_\-REG~POCR1RAL}\label{ATmega32M1_8h_b20d40d08b096adffaafc445cb232161}




Definition at line 125 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-8\_\-REG@{POCR1RA\_\-8\_\-REG}}
\index{POCR1RA\_\-8\_\-REG@{POCR1RA\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-8\_\-REG~POCR1RAH}\label{ATmega32M1_8h_52475c00894d607c8f908cebcca8756e}




Definition at line 138 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1RA\_\-9\_\-REG@{POCR1RA\_\-9\_\-REG}}
\index{POCR1RA\_\-9\_\-REG@{POCR1RA\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1RA\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1RA\_\-9\_\-REG~POCR1RAH}\label{ATmega32M1_8h_33c595eb7dff46c9a0cdb14981266ef3}




Definition at line 139 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-00\_\-REG@{POCR1SA\_\-00\_\-REG}}
\index{POCR1SA\_\-00\_\-REG@{POCR1SA\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-00\_\-REG~POCR1SAH}\label{ATmega32M1_8h_e407dcdbf047564858795731e8dbe738}




Definition at line 434 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-01\_\-REG@{POCR1SA\_\-01\_\-REG}}
\index{POCR1SA\_\-01\_\-REG@{POCR1SA\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-01\_\-REG~POCR1SAH}\label{ATmega32M1_8h_63f6082d6f2b26d5452c1b834d1d0efc}




Definition at line 435 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-0\_\-REG@{POCR1SA\_\-0\_\-REG}}
\index{POCR1SA\_\-0\_\-REG@{POCR1SA\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-0\_\-REG~POCR1SAL}\label{ATmega32M1_8h_b3dc5b146f49af7eec4fe84b3198520f}




Definition at line 438 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-1\_\-REG@{POCR1SA\_\-1\_\-REG}}
\index{POCR1SA\_\-1\_\-REG@{POCR1SA\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-1\_\-REG~POCR1SAL}\label{ATmega32M1_8h_76a1026f98d2779de9579cf70d4ba5da}




Definition at line 439 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-2\_\-REG@{POCR1SA\_\-2\_\-REG}}
\index{POCR1SA\_\-2\_\-REG@{POCR1SA\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-2\_\-REG~POCR1SAL}\label{ATmega32M1_8h_2e9c669b07f15b855e6d968396885015}




Definition at line 440 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-3\_\-REG@{POCR1SA\_\-3\_\-REG}}
\index{POCR1SA\_\-3\_\-REG@{POCR1SA\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-3\_\-REG~POCR1SAL}\label{ATmega32M1_8h_215f2a163566a363878abb13373e0f47}




Definition at line 441 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-4\_\-REG@{POCR1SA\_\-4\_\-REG}}
\index{POCR1SA\_\-4\_\-REG@{POCR1SA\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-4\_\-REG~POCR1SAL}\label{ATmega32M1_8h_e0dbf8fd8446355619bcc5508e98c946}




Definition at line 442 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-5\_\-REG@{POCR1SA\_\-5\_\-REG}}
\index{POCR1SA\_\-5\_\-REG@{POCR1SA\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-5\_\-REG~POCR1SAL}\label{ATmega32M1_8h_1b6dd8e9904eb2ae4eb2b1849b25b199}




Definition at line 443 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-6\_\-REG@{POCR1SA\_\-6\_\-REG}}
\index{POCR1SA\_\-6\_\-REG@{POCR1SA\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-6\_\-REG~POCR1SAL}\label{ATmega32M1_8h_949705548db19e6d8809a1b6b38b79a5}




Definition at line 444 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-7\_\-REG@{POCR1SA\_\-7\_\-REG}}
\index{POCR1SA\_\-7\_\-REG@{POCR1SA\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-7\_\-REG~POCR1SAL}\label{ATmega32M1_8h_89d8b78cdd75506f0ea599266a1f7197}




Definition at line 445 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-8\_\-REG@{POCR1SA\_\-8\_\-REG}}
\index{POCR1SA\_\-8\_\-REG@{POCR1SA\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-8\_\-REG~POCR1SAH}\label{ATmega32M1_8h_92d98f0facdaa32a34e50c89a1b0c1b9}




Definition at line 432 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SA\_\-9\_\-REG@{POCR1SA\_\-9\_\-REG}}
\index{POCR1SA\_\-9\_\-REG@{POCR1SA\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SA\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SA\_\-9\_\-REG~POCR1SAH}\label{ATmega32M1_8h_22bff4c619b2bbffb7e83a7bed67d30a}




Definition at line 433 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-00\_\-REG@{POCR1SB\_\-00\_\-REG}}
\index{POCR1SB\_\-00\_\-REG@{POCR1SB\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-00\_\-REG~POCR1SBH}\label{ATmega32M1_8h_8882ba193dfc96c3b3217126824477f0}




Definition at line 888 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-01\_\-REG@{POCR1SB\_\-01\_\-REG}}
\index{POCR1SB\_\-01\_\-REG@{POCR1SB\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-01\_\-REG~POCR1SBH}\label{ATmega32M1_8h_f4ab2beb433926242864605c54583f38}




Definition at line 889 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-0\_\-REG@{POCR1SB\_\-0\_\-REG}}
\index{POCR1SB\_\-0\_\-REG@{POCR1SB\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-0\_\-REG~POCR1SBL}\label{ATmega32M1_8h_ee0b4817eea2178a15754347719e8740}




Definition at line 865 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-1\_\-REG@{POCR1SB\_\-1\_\-REG}}
\index{POCR1SB\_\-1\_\-REG@{POCR1SB\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-1\_\-REG~POCR1SBL}\label{ATmega32M1_8h_4911f8b72fb74c9a5930e7e0473c6690}




Definition at line 866 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-2\_\-REG@{POCR1SB\_\-2\_\-REG}}
\index{POCR1SB\_\-2\_\-REG@{POCR1SB\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-2\_\-REG~POCR1SBL}\label{ATmega32M1_8h_45f8bcd00ca4663fb7a3c9a7812f18af}




Definition at line 867 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-3\_\-REG@{POCR1SB\_\-3\_\-REG}}
\index{POCR1SB\_\-3\_\-REG@{POCR1SB\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-3\_\-REG~POCR1SBL}\label{ATmega32M1_8h_c05eaa59f45df97602a2e17416e7d35a}




Definition at line 868 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-4\_\-REG@{POCR1SB\_\-4\_\-REG}}
\index{POCR1SB\_\-4\_\-REG@{POCR1SB\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-4\_\-REG~POCR1SBL}\label{ATmega32M1_8h_f94bb1ae16e3f85bb9df677e9f98ee17}




Definition at line 869 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-5\_\-REG@{POCR1SB\_\-5\_\-REG}}
\index{POCR1SB\_\-5\_\-REG@{POCR1SB\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-5\_\-REG~POCR1SBL}\label{ATmega32M1_8h_0594898badde63c4547006c0b77f0faf}




Definition at line 870 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-6\_\-REG@{POCR1SB\_\-6\_\-REG}}
\index{POCR1SB\_\-6\_\-REG@{POCR1SB\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-6\_\-REG~POCR1SBL}\label{ATmega32M1_8h_88e8d85744e1a406aa807f79470829f4}




Definition at line 871 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-7\_\-REG@{POCR1SB\_\-7\_\-REG}}
\index{POCR1SB\_\-7\_\-REG@{POCR1SB\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-7\_\-REG~POCR1SBL}\label{ATmega32M1_8h_d898e79705c60a307b7c283648907916}




Definition at line 872 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-8\_\-REG@{POCR1SB\_\-8\_\-REG}}
\index{POCR1SB\_\-8\_\-REG@{POCR1SB\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-8\_\-REG~POCR1SBH}\label{ATmega32M1_8h_509aad6e9986ea0ef015a556afaf0a2d}




Definition at line 886 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR1SB\_\-9\_\-REG@{POCR1SB\_\-9\_\-REG}}
\index{POCR1SB\_\-9\_\-REG@{POCR1SB\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR1SB\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR1SB\_\-9\_\-REG~POCR1SBH}\label{ATmega32M1_8h_c521149a90376b130f838343aedd8b77}




Definition at line 887 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-00\_\-REG@{POCR2RA\_\-00\_\-REG}}
\index{POCR2RA\_\-00\_\-REG@{POCR2RA\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-00\_\-REG~POCR2RAH}\label{ATmega32M1_8h_9eb2c2a03d8a322ea0f4afc1597205cf}




Definition at line 421 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-01\_\-REG@{POCR2RA\_\-01\_\-REG}}
\index{POCR2RA\_\-01\_\-REG@{POCR2RA\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-01\_\-REG~POCR2RAH}\label{ATmega32M1_8h_5398006fb65c444cf9cfab7fbe0a8635}




Definition at line 422 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-0\_\-REG@{POCR2RA\_\-0\_\-REG}}
\index{POCR2RA\_\-0\_\-REG@{POCR2RA\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-0\_\-REG~POCR2RAL}\label{ATmega32M1_8h_0ab571d645d80c260bfad8b6ab599e82}




Definition at line 390 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-1\_\-REG@{POCR2RA\_\-1\_\-REG}}
\index{POCR2RA\_\-1\_\-REG@{POCR2RA\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-1\_\-REG~POCR2RAL}\label{ATmega32M1_8h_cb0b462ea1d987a7989b2bb6027d58c1}




Definition at line 391 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-2\_\-REG@{POCR2RA\_\-2\_\-REG}}
\index{POCR2RA\_\-2\_\-REG@{POCR2RA\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-2\_\-REG~POCR2RAL}\label{ATmega32M1_8h_09a460c70981d8495703d0726c32f630}




Definition at line 392 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-3\_\-REG@{POCR2RA\_\-3\_\-REG}}
\index{POCR2RA\_\-3\_\-REG@{POCR2RA\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-3\_\-REG~POCR2RAL}\label{ATmega32M1_8h_5195fd854caba3265a46a6ec396fa841}




Definition at line 393 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-4\_\-REG@{POCR2RA\_\-4\_\-REG}}
\index{POCR2RA\_\-4\_\-REG@{POCR2RA\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-4\_\-REG~POCR2RAL}\label{ATmega32M1_8h_f68b99d06e1546bc0f8f1680fadd89a6}




Definition at line 394 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-5\_\-REG@{POCR2RA\_\-5\_\-REG}}
\index{POCR2RA\_\-5\_\-REG@{POCR2RA\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-5\_\-REG~POCR2RAL}\label{ATmega32M1_8h_ddd0e2249fefea8825cc222e33ebed81}




Definition at line 395 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-6\_\-REG@{POCR2RA\_\-6\_\-REG}}
\index{POCR2RA\_\-6\_\-REG@{POCR2RA\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-6\_\-REG~POCR2RAL}\label{ATmega32M1_8h_02d78a8834354a89e7f900cb541c038e}




Definition at line 396 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-7\_\-REG@{POCR2RA\_\-7\_\-REG}}
\index{POCR2RA\_\-7\_\-REG@{POCR2RA\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-7\_\-REG~POCR2RAL}\label{ATmega32M1_8h_9318b72fbbc209f2eab0c7d04d13ca3c}




Definition at line 397 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-8\_\-REG@{POCR2RA\_\-8\_\-REG}}
\index{POCR2RA\_\-8\_\-REG@{POCR2RA\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-8\_\-REG~POCR2RAH}\label{ATmega32M1_8h_8791537cdb6cb57a2b751b3ec1306415}




Definition at line 419 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2RA\_\-9\_\-REG@{POCR2RA\_\-9\_\-REG}}
\index{POCR2RA\_\-9\_\-REG@{POCR2RA\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2RA\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2RA\_\-9\_\-REG~POCR2RAH}\label{ATmega32M1_8h_541d9294e7081569a0fba855a4bdf619}




Definition at line 420 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-00\_\-REG@{POCR2SA\_\-00\_\-REG}}
\index{POCR2SA\_\-00\_\-REG@{POCR2SA\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-00\_\-REG~POCR2SAH}\label{ATmega32M1_8h_efe15e4799e284e55ebb2b77a0a03b91}




Definition at line 692 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-01\_\-REG@{POCR2SA\_\-01\_\-REG}}
\index{POCR2SA\_\-01\_\-REG@{POCR2SA\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-01\_\-REG~POCR2SAH}\label{ATmega32M1_8h_4036c763c7073309b6c687b2a1471869}




Definition at line 693 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-0\_\-REG@{POCR2SA\_\-0\_\-REG}}
\index{POCR2SA\_\-0\_\-REG@{POCR2SA\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-0\_\-REG~POCR2SAL}\label{ATmega32M1_8h_cc5e81556049f65b46b9c6b21c977c1c}




Definition at line 696 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-1\_\-REG@{POCR2SA\_\-1\_\-REG}}
\index{POCR2SA\_\-1\_\-REG@{POCR2SA\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-1\_\-REG~POCR2SAL}\label{ATmega32M1_8h_c4a6ebf6b8215d993dbf8d45ec220f88}




Definition at line 697 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-2\_\-REG@{POCR2SA\_\-2\_\-REG}}
\index{POCR2SA\_\-2\_\-REG@{POCR2SA\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-2\_\-REG~POCR2SAL}\label{ATmega32M1_8h_5507fb20ba66d4819b0c48edc4b8fcd2}




Definition at line 698 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-3\_\-REG@{POCR2SA\_\-3\_\-REG}}
\index{POCR2SA\_\-3\_\-REG@{POCR2SA\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-3\_\-REG~POCR2SAL}\label{ATmega32M1_8h_d71893c57158194a635ad771562aefd7}




Definition at line 699 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-4\_\-REG@{POCR2SA\_\-4\_\-REG}}
\index{POCR2SA\_\-4\_\-REG@{POCR2SA\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-4\_\-REG~POCR2SAL}\label{ATmega32M1_8h_4f988f9924c3c32328f34544003c1e7a}




Definition at line 700 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-5\_\-REG@{POCR2SA\_\-5\_\-REG}}
\index{POCR2SA\_\-5\_\-REG@{POCR2SA\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-5\_\-REG~POCR2SAL}\label{ATmega32M1_8h_ea56a5cdc16dab45b6bfd4d11fca9317}




Definition at line 701 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-6\_\-REG@{POCR2SA\_\-6\_\-REG}}
\index{POCR2SA\_\-6\_\-REG@{POCR2SA\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-6\_\-REG~POCR2SAL}\label{ATmega32M1_8h_a6ed39a9d0b7db811d20a7ffe1bf8aff}




Definition at line 702 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-7\_\-REG@{POCR2SA\_\-7\_\-REG}}
\index{POCR2SA\_\-7\_\-REG@{POCR2SA\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-7\_\-REG~POCR2SAL}\label{ATmega32M1_8h_daea5e0fce7c17e2d76803235698dba7}




Definition at line 703 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-8\_\-REG@{POCR2SA\_\-8\_\-REG}}
\index{POCR2SA\_\-8\_\-REG@{POCR2SA\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-8\_\-REG~POCR2SAH}\label{ATmega32M1_8h_80243ba978473fbd84bbe449425aef41}




Definition at line 690 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SA\_\-9\_\-REG@{POCR2SA\_\-9\_\-REG}}
\index{POCR2SA\_\-9\_\-REG@{POCR2SA\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SA\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SA\_\-9\_\-REG~POCR2SAH}\label{ATmega32M1_8h_68f5f9b07536ced69b0f7e2d145bce97}




Definition at line 691 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-00\_\-REG@{POCR2SB\_\-00\_\-REG}}
\index{POCR2SB\_\-00\_\-REG@{POCR2SB\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-00\_\-REG~POCR2SBH}\label{ATmega32M1_8h_5fa90e0d9cd0a757988dc1003298ed4c}




Definition at line 213 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-01\_\-REG@{POCR2SB\_\-01\_\-REG}}
\index{POCR2SB\_\-01\_\-REG@{POCR2SB\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-01\_\-REG~POCR2SBH}\label{ATmega32M1_8h_c9f75bcfa2f11f6f854c2a92d3108b7a}




Definition at line 214 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-0\_\-REG@{POCR2SB\_\-0\_\-REG}}
\index{POCR2SB\_\-0\_\-REG@{POCR2SB\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-0\_\-REG~POCR2SBL}\label{ATmega32M1_8h_0b05a5cb6d245b4493a9cdf465ef505e}




Definition at line 196 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-1\_\-REG@{POCR2SB\_\-1\_\-REG}}
\index{POCR2SB\_\-1\_\-REG@{POCR2SB\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-1\_\-REG~POCR2SBL}\label{ATmega32M1_8h_0d3723d1c9822d213e36020a9166d267}




Definition at line 197 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-2\_\-REG@{POCR2SB\_\-2\_\-REG}}
\index{POCR2SB\_\-2\_\-REG@{POCR2SB\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-2\_\-REG~POCR2SBL}\label{ATmega32M1_8h_6e5db301423b83d1bd91d6c303d3d8e5}




Definition at line 198 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-3\_\-REG@{POCR2SB\_\-3\_\-REG}}
\index{POCR2SB\_\-3\_\-REG@{POCR2SB\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-3\_\-REG~POCR2SBL}\label{ATmega32M1_8h_a701b3de1cb78fbede49276a481488db}




Definition at line 199 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-4\_\-REG@{POCR2SB\_\-4\_\-REG}}
\index{POCR2SB\_\-4\_\-REG@{POCR2SB\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-4\_\-REG~POCR2SBL}\label{ATmega32M1_8h_969f12b183b7902eb82fa38f74148842}




Definition at line 200 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-5\_\-REG@{POCR2SB\_\-5\_\-REG}}
\index{POCR2SB\_\-5\_\-REG@{POCR2SB\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-5\_\-REG~POCR2SBL}\label{ATmega32M1_8h_25140544e463e48b60840ef740b388a1}




Definition at line 201 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-6\_\-REG@{POCR2SB\_\-6\_\-REG}}
\index{POCR2SB\_\-6\_\-REG@{POCR2SB\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-6\_\-REG~POCR2SBL}\label{ATmega32M1_8h_2b70083563aeb8ed593abd10f2cee3c5}




Definition at line 202 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-7\_\-REG@{POCR2SB\_\-7\_\-REG}}
\index{POCR2SB\_\-7\_\-REG@{POCR2SB\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-7\_\-REG~POCR2SBL}\label{ATmega32M1_8h_ae3724c4512388d3d4d7d8766b489c72}




Definition at line 203 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-8\_\-REG@{POCR2SB\_\-8\_\-REG}}
\index{POCR2SB\_\-8\_\-REG@{POCR2SB\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-8\_\-REG~POCR2SBH}\label{ATmega32M1_8h_1cab49cb6c4a8a92417e40f02ae5f51f}




Definition at line 211 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR2SB\_\-9\_\-REG@{POCR2SB\_\-9\_\-REG}}
\index{POCR2SB\_\-9\_\-REG@{POCR2SB\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR2SB\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR2SB\_\-9\_\-REG~POCR2SBH}\label{ATmega32M1_8h_0282a3be66341967331082bf1c61ec56}




Definition at line 212 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-00\_\-REG@{POCR\_\-RB\_\-00\_\-REG}}
\index{POCR\_\-RB\_\-00\_\-REG@{POCR\_\-RB\_\-00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-00\_\-REG~POCR\_\-RBH}\label{ATmega32M1_8h_caa43bcb09d627d30ba7ebcda6b264a5}




Definition at line 956 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-01\_\-REG@{POCR\_\-RB\_\-01\_\-REG}}
\index{POCR\_\-RB\_\-01\_\-REG@{POCR\_\-RB\_\-01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-01\_\-REG~POCR\_\-RBH}\label{ATmega32M1_8h_b2fcb2a7dd08d6f32b98b8fba3eaef4f}




Definition at line 957 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-0\_\-REG@{POCR\_\-RB\_\-0\_\-REG}}
\index{POCR\_\-RB\_\-0\_\-REG@{POCR\_\-RB\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-0\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_1ef7b247171311d51fb444b7a6a5dbb7}




Definition at line 934 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-1\_\-REG@{POCR\_\-RB\_\-1\_\-REG}}
\index{POCR\_\-RB\_\-1\_\-REG@{POCR\_\-RB\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-1\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_7936aa174087cc0a382439f6500d49da}




Definition at line 935 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-2\_\-REG@{POCR\_\-RB\_\-2\_\-REG}}
\index{POCR\_\-RB\_\-2\_\-REG@{POCR\_\-RB\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-2\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_6a4f56118e14cbaf0cd912f3d98d52f3}




Definition at line 936 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-3\_\-REG@{POCR\_\-RB\_\-3\_\-REG}}
\index{POCR\_\-RB\_\-3\_\-REG@{POCR\_\-RB\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-3\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_f636bb5005224bcad6ae2952fa04fdef}




Definition at line 937 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-4\_\-REG@{POCR\_\-RB\_\-4\_\-REG}}
\index{POCR\_\-RB\_\-4\_\-REG@{POCR\_\-RB\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-4\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_4970de6ddb3fd5acab559cbb30a3bf71}




Definition at line 938 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-5\_\-REG@{POCR\_\-RB\_\-5\_\-REG}}
\index{POCR\_\-RB\_\-5\_\-REG@{POCR\_\-RB\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-5\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_4ccc374a77d5d08001ee26c384660d0a}




Definition at line 939 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-6\_\-REG@{POCR\_\-RB\_\-6\_\-REG}}
\index{POCR\_\-RB\_\-6\_\-REG@{POCR\_\-RB\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-6\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_a25ef80e203046af55bcb084b3d5ab05}




Definition at line 940 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-7\_\-REG@{POCR\_\-RB\_\-7\_\-REG}}
\index{POCR\_\-RB\_\-7\_\-REG@{POCR\_\-RB\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-7\_\-REG~POCR\_\-RBL}\label{ATmega32M1_8h_9063cc50635a7a675f71d843340d32a9}




Definition at line 941 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-8\_\-REG@{POCR\_\-RB\_\-8\_\-REG}}
\index{POCR\_\-RB\_\-8\_\-REG@{POCR\_\-RB\_\-8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-8\_\-REG~POCR\_\-RBH}\label{ATmega32M1_8h_9eb6e7bad39734128caca675cfc65b4f}




Definition at line 954 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POCR\_\-RB\_\-9\_\-REG@{POCR\_\-RB\_\-9\_\-REG}}
\index{POCR\_\-RB\_\-9\_\-REG@{POCR\_\-RB\_\-9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POCR\_\-RB\_\-9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POCR\_\-RB\_\-9\_\-REG~POCR\_\-RBH}\label{ATmega32M1_8h_21b88017277a045e2013fa3fee50e698}




Definition at line 955 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POEN0A\_\-REG@{POEN0A\_\-REG}}
\index{POEN0A\_\-REG@{POEN0A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POEN0A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POEN0A\_\-REG~POC}\label{ATmega32M1_8h_feecc949dbd1eedcfe44e8a71b4b8801}




Definition at line 1122 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POEN0B\_\-REG@{POEN0B\_\-REG}}
\index{POEN0B\_\-REG@{POEN0B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POEN0B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POEN0B\_\-REG~POC}\label{ATmega32M1_8h_41b99216fb786a9ba10dd047f51c469b}




Definition at line 1123 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POEN1A\_\-REG@{POEN1A\_\-REG}}
\index{POEN1A\_\-REG@{POEN1A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POEN1A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POEN1A\_\-REG~POC}\label{ATmega32M1_8h_648861d04298693dbdb31d32da7cd7b8}




Definition at line 1124 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POEN1B\_\-REG@{POEN1B\_\-REG}}
\index{POEN1B\_\-REG@{POEN1B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POEN1B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POEN1B\_\-REG~POC}\label{ATmega32M1_8h_41f1af76d5c84def88791b5e853e7237}




Definition at line 1125 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POEN2A\_\-REG@{POEN2A\_\-REG}}
\index{POEN2A\_\-REG@{POEN2A\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POEN2A\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POEN2A\_\-REG~POC}\label{ATmega32M1_8h_139b3985c28185bdb587c8f39260aa37}




Definition at line 1126 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POEN2B\_\-REG@{POEN2B\_\-REG}}
\index{POEN2B\_\-REG@{POEN2B\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POEN2B\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POEN2B\_\-REG~POC}\label{ATmega32M1_8h_9e129043aa869b33891aeebb945e8538}




Definition at line 1127 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POPA\_\-REG@{POPA\_\-REG}}
\index{POPA\_\-REG@{POPA\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POPA\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POPA\_\-REG~PCNF}\label{ATmega32M1_8h_4385a4e2495219369e04ff14edfd2508}




Definition at line 1140 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POPB\_\-REG@{POPB\_\-REG}}
\index{POPB\_\-REG@{POPB\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POPB\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POPB\_\-REG~PCNF}\label{ATmega32M1_8h_16d8370add11e8935c92c8f432e477fb}




Definition at line 1141 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORF\_\-REG@{PORF\_\-REG}}
\index{PORF\_\-REG@{PORF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORF\_\-REG~MCUSR}\label{ATmega32M1_8h_4793c8733c88789e4b47f72f77323fee}




Definition at line 851 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB0\_\-REG@{PORTB0\_\-REG}}
\index{PORTB0\_\-REG@{PORTB0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB0\_\-REG~PORTB}\label{ATmega32M1_8h_814e08d4ce55f8ef9f191bf2d2bb2242}




Definition at line 99 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB1\_\-REG@{PORTB1\_\-REG}}
\index{PORTB1\_\-REG@{PORTB1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB1\_\-REG~PORTB}\label{ATmega32M1_8h_3eadaad1e12b199a95c7b50317ed4a74}




Definition at line 100 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB2\_\-REG@{PORTB2\_\-REG}}
\index{PORTB2\_\-REG@{PORTB2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB2\_\-REG~PORTB}\label{ATmega32M1_8h_ea22c0fcf453c2cfed4b484d7dbdd012}




Definition at line 101 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB3\_\-REG@{PORTB3\_\-REG}}
\index{PORTB3\_\-REG@{PORTB3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB3\_\-REG~PORTB}\label{ATmega32M1_8h_3f3db80ab2df6227b50dcc9167dde63b}




Definition at line 102 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB4\_\-REG@{PORTB4\_\-REG}}
\index{PORTB4\_\-REG@{PORTB4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB4\_\-REG~PORTB}\label{ATmega32M1_8h_4d2fae120a0ebd695b8ffc6a18abf574}




Definition at line 103 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB5\_\-REG@{PORTB5\_\-REG}}
\index{PORTB5\_\-REG@{PORTB5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB5\_\-REG~PORTB}\label{ATmega32M1_8h_cbf5541cd8cce15b3d335ec1bb9c6674}




Definition at line 104 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB6\_\-REG@{PORTB6\_\-REG}}
\index{PORTB6\_\-REG@{PORTB6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB6\_\-REG~PORTB}\label{ATmega32M1_8h_ed9d497eb6d695e499fc490bbc9149fc}




Definition at line 105 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTB7\_\-REG@{PORTB7\_\-REG}}
\index{PORTB7\_\-REG@{PORTB7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTB7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTB7\_\-REG~PORTB}\label{ATmega32M1_8h_c83c2727ee2a47574b83f215c21be623}




Definition at line 106 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC0\_\-REG@{PORTC0\_\-REG}}
\index{PORTC0\_\-REG@{PORTC0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC0\_\-REG~PORTC}\label{ATmega32M1_8h_5d396cb8a677196f22e78ed6e10b9a84}




Definition at line 329 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC1\_\-REG@{PORTC1\_\-REG}}
\index{PORTC1\_\-REG@{PORTC1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC1\_\-REG~PORTC}\label{ATmega32M1_8h_e66f8f820a4dbc9eafa90e19164b75ea}




Definition at line 330 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC2\_\-REG@{PORTC2\_\-REG}}
\index{PORTC2\_\-REG@{PORTC2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC2\_\-REG~PORTC}\label{ATmega32M1_8h_855339e43f8c9fa5decf424bf7b22efb}




Definition at line 331 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC3\_\-REG@{PORTC3\_\-REG}}
\index{PORTC3\_\-REG@{PORTC3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC3\_\-REG~PORTC}\label{ATmega32M1_8h_e566336740604af7886c8ac746c3d01d}




Definition at line 332 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC4\_\-REG@{PORTC4\_\-REG}}
\index{PORTC4\_\-REG@{PORTC4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC4\_\-REG~PORTC}\label{ATmega32M1_8h_897deb29e12652f468cfdb16b9e2545d}




Definition at line 333 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC5\_\-REG@{PORTC5\_\-REG}}
\index{PORTC5\_\-REG@{PORTC5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC5\_\-REG~PORTC}\label{ATmega32M1_8h_36161b90f5b63a3c633c3a8b5679bc04}




Definition at line 334 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC6\_\-REG@{PORTC6\_\-REG}}
\index{PORTC6\_\-REG@{PORTC6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC6\_\-REG~PORTC}\label{ATmega32M1_8h_7350f2d4d0b19f13d886f6cdd860413d}




Definition at line 335 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTC7\_\-REG@{PORTC7\_\-REG}}
\index{PORTC7\_\-REG@{PORTC7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTC7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTC7\_\-REG~PORTC}\label{ATmega32M1_8h_e18de085d02b4eddba5c0de0f6afb9a7}




Definition at line 336 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD0\_\-REG@{PORTD0\_\-REG}}
\index{PORTD0\_\-REG@{PORTD0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD0\_\-REG~PORTD}\label{ATmega32M1_8h_2952ce2f503b50c06170b7b28e69ea6e}




Definition at line 304 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD1\_\-REG@{PORTD1\_\-REG}}
\index{PORTD1\_\-REG@{PORTD1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD1\_\-REG~PORTD}\label{ATmega32M1_8h_1f188cc9d7fdd39ba485f47f778927db}




Definition at line 305 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD2\_\-REG@{PORTD2\_\-REG}}
\index{PORTD2\_\-REG@{PORTD2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD2\_\-REG~PORTD}\label{ATmega32M1_8h_dff64c25b54afb91614458b290c48d8c}




Definition at line 306 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD3\_\-REG@{PORTD3\_\-REG}}
\index{PORTD3\_\-REG@{PORTD3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD3\_\-REG~PORTD}\label{ATmega32M1_8h_f1adf662f9735f2de8c6a55ee9bbed6b}




Definition at line 307 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD4\_\-REG@{PORTD4\_\-REG}}
\index{PORTD4\_\-REG@{PORTD4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD4\_\-REG~PORTD}\label{ATmega32M1_8h_f9a7e7598eb580f426478437fc0047e9}




Definition at line 308 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD5\_\-REG@{PORTD5\_\-REG}}
\index{PORTD5\_\-REG@{PORTD5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD5\_\-REG~PORTD}\label{ATmega32M1_8h_8ba06670096d230e69feab9a7168635f}




Definition at line 309 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD6\_\-REG@{PORTD6\_\-REG}}
\index{PORTD6\_\-REG@{PORTD6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD6\_\-REG~PORTD}\label{ATmega32M1_8h_ad804d4f338cac9a1ec917d2ffeafeca}




Definition at line 310 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTD7\_\-REG@{PORTD7\_\-REG}}
\index{PORTD7\_\-REG@{PORTD7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTD7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTD7\_\-REG~PORTD}\label{ATmega32M1_8h_60aee315b1008ef95582a7a1812ce6c5}




Definition at line 311 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTE0\_\-REG@{PORTE0\_\-REG}}
\index{PORTE0\_\-REG@{PORTE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTE0\_\-REG~PORTE}\label{ATmega32M1_8h_b854bacbc9db551612ffea38c0fe1a52}




Definition at line 314 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTE1\_\-REG@{PORTE1\_\-REG}}
\index{PORTE1\_\-REG@{PORTE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTE1\_\-REG~PORTE}\label{ATmega32M1_8h_7727169dc9b8a68df9a9a7196ab72e58}




Definition at line 315 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PORTE2\_\-REG@{PORTE2\_\-REG}}
\index{PORTE2\_\-REG@{PORTE2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PORTE2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PORTE2\_\-REG~PORTE}\label{ATmega32M1_8h_14f364293995984d75f193b593cd4a40}




Definition at line 316 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POVEN0\_\-REG@{POVEN0\_\-REG}}
\index{POVEN0\_\-REG@{POVEN0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POVEN0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POVEN0\_\-REG~PMIC0}\label{ATmega32M1_8h_33f4764ddcec584e5cf733c858c882c7}




Definition at line 1110 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POVEN1\_\-REG@{POVEN1\_\-REG}}
\index{POVEN1\_\-REG@{POVEN1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POVEN1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POVEN1\_\-REG~PMIC1}\label{ATmega32M1_8h_707782491a204515fa687d44dbba5324}




Definition at line 528 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!POVEN2\_\-REG@{POVEN2\_\-REG}}
\index{POVEN2\_\-REG@{POVEN2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[POVEN2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define POVEN2\_\-REG~PMIC2}\label{ATmega32M1_8h_8614f841a432ae6e3235df8473afefb9}




Definition at line 514 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PPRE0\_\-REG@{PPRE0\_\-REG}}
\index{PPRE0\_\-REG@{PPRE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PPRE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PPRE0\_\-REG~PCTL}\label{ATmega32M1_8h_67aa5c6d900f3f889634bde721d37620}




Definition at line 553 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PPRE1\_\-REG@{PPRE1\_\-REG}}
\index{PPRE1\_\-REG@{PPRE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PPRE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PPRE1\_\-REG~PCTL}\label{ATmega32M1_8h_1a4a86ad5a077aa2ccf63243a5865620}




Definition at line 554 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRADC\_\-REG@{PRADC\_\-REG}}
\index{PRADC\_\-REG@{PRADC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRADC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRADC\_\-REG~PRR}\label{ATmega32M1_8h_d0f5125c0625364b0ee920b1390d9f87}




Definition at line 247 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRCAN\_\-REG@{PRCAN\_\-REG}}
\index{PRCAN\_\-REG@{PRCAN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRCAN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRCAN\_\-REG~PRR}\label{ATmega32M1_8h_275c9fbf34df0f812b66551ab62fe56d}




Definition at line 253 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM00\_\-REG@{PRFM00\_\-REG}}
\index{PRFM00\_\-REG@{PRFM00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM00\_\-REG~PMIC0}\label{ATmega32M1_8h_1ea1da96ae8cef1fa04b043612d9eb48}




Definition at line 1103 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM01\_\-REG@{PRFM01\_\-REG}}
\index{PRFM01\_\-REG@{PRFM01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM01\_\-REG~PMIC0}\label{ATmega32M1_8h_85b230a152f8382928a610523f975e1c}




Definition at line 1104 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM02\_\-REG@{PRFM02\_\-REG}}
\index{PRFM02\_\-REG@{PRFM02\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM02\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM02\_\-REG~PMIC0}\label{ATmega32M1_8h_f9ca394a428f2f5b4a52a53d20bf3196}




Definition at line 1105 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM10\_\-REG@{PRFM10\_\-REG}}
\index{PRFM10\_\-REG@{PRFM10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM10\_\-REG~PMIC1}\label{ATmega32M1_8h_0bd7fd16115bf7708e9e564a72e93d9c}




Definition at line 521 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM11\_\-REG@{PRFM11\_\-REG}}
\index{PRFM11\_\-REG@{PRFM11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM11\_\-REG~PMIC1}\label{ATmega32M1_8h_e2b5a6be6a08a22c18f3d3eccc26690d}




Definition at line 522 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM12\_\-REG@{PRFM12\_\-REG}}
\index{PRFM12\_\-REG@{PRFM12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM12\_\-REG~PMIC1}\label{ATmega32M1_8h_69c0a2e1c1fd3a062643c2804f17b8b2}




Definition at line 523 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM20\_\-REG@{PRFM20\_\-REG}}
\index{PRFM20\_\-REG@{PRFM20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM20\_\-REG~PMIC2}\label{ATmega32M1_8h_61848c997f568c992f18cb805e8a2b5e}




Definition at line 507 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM21\_\-REG@{PRFM21\_\-REG}}
\index{PRFM21\_\-REG@{PRFM21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM21\_\-REG~PMIC2}\label{ATmega32M1_8h_fdb56b5abcb051939b147c2617b76603}




Definition at line 508 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRFM22\_\-REG@{PRFM22\_\-REG}}
\index{PRFM22\_\-REG@{PRFM22\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRFM22\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRFM22\_\-REG~PMIC2}\label{ATmega32M1_8h_724ae68dbfe1056c8f21c873950a217f}




Definition at line 509 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRLIN\_\-REG@{PRLIN\_\-REG}}
\index{PRLIN\_\-REG@{PRLIN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRLIN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRLIN\_\-REG~PRR}\label{ATmega32M1_8h_55436b2bf914618d452cd727e9c919e9}




Definition at line 248 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRPSC\_\-REG@{PRPSC\_\-REG}}
\index{PRPSC\_\-REG@{PRPSC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRPSC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRPSC\_\-REG~PRR}\label{ATmega32M1_8h_1937300e495eb4b3a345816e12145c4e}




Definition at line 252 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRS0\_\-REG@{PRS0\_\-REG}}
\index{PRS0\_\-REG@{PRS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRS0\_\-REG~CANBT2}\label{ATmega32M1_8h_6a78210973f3302aa10f92fde2eda262}




Definition at line 1146 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRS1\_\-REG@{PRS1\_\-REG}}
\index{PRS1\_\-REG@{PRS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRS1\_\-REG~CANBT2}\label{ATmega32M1_8h_281246accda92544ac368915644a2d52}




Definition at line 1147 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRS2\_\-REG@{PRS2\_\-REG}}
\index{PRS2\_\-REG@{PRS2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRS2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRS2\_\-REG~CANBT2}\label{ATmega32M1_8h_5c5895152be890af9134642abfb3693f}




Definition at line 1148 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRSPI\_\-REG@{PRSPI\_\-REG}}
\index{PRSPI\_\-REG@{PRSPI\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRSPI\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRSPI\_\-REG~PRR}\label{ATmega32M1_8h_405188b225f677e63443df42562cb6f4}




Definition at line 249 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRTIM0\_\-REG@{PRTIM0\_\-REG}}
\index{PRTIM0\_\-REG@{PRTIM0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRTIM0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRTIM0\_\-REG~PRR}\label{ATmega32M1_8h_383cbcdc57f174082da252908e8d8b7e}




Definition at line 250 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRTIM1\_\-REG@{PRTIM1\_\-REG}}
\index{PRTIM1\_\-REG@{PRTIM1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRTIM1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRTIM1\_\-REG~PRR}\label{ATmega32M1_8h_e6b05a19b01448d75b81c43eafa77f7b}




Definition at line 251 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PRUN\_\-REG@{PRUN\_\-REG}}
\index{PRUN\_\-REG@{PRUN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PRUN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PRUN\_\-REG~PCTL}\label{ATmega32M1_8h_92055389d6d39c0a1f8418e5b3c14887}




Definition at line 550 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCIN0\_\-BIT@{PSCIN0\_\-BIT}}
\index{PSCIN0\_\-BIT@{PSCIN0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCIN0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCIN0\_\-BIT~1}\label{ATmega32M1_8h_b844af811a01a6588bbd356253b6de1b}




Definition at line 1470 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCIN0\_\-PORT@{PSCIN0\_\-PORT}}
\index{PSCIN0\_\-PORT@{PSCIN0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCIN0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCIN0\_\-PORT~PORTD}\label{ATmega32M1_8h_3e133de53f0f82c3961dd61cae8af665}




Definition at line 1469 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCIN1\_\-BIT@{PSCIN1\_\-BIT}}
\index{PSCIN1\_\-BIT@{PSCIN1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCIN1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCIN1\_\-BIT~1}\label{ATmega32M1_8h_d36dd8b4c496e0132289dadfaa6525a6}




Definition at line 1408 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCIN1\_\-PORT@{PSCIN1\_\-PORT}}
\index{PSCIN1\_\-PORT@{PSCIN1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCIN1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCIN1\_\-PORT~PORTC}\label{ATmega32M1_8h_fda9713a53d957c6d14721f8545edd4d}




Definition at line 1407 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCIN2\_\-BIT@{PSCIN2\_\-BIT}}
\index{PSCIN2\_\-BIT@{PSCIN2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCIN2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCIN2\_\-BIT~2}\label{ATmega32M1_8h_e1fc43a0ff5eaffba53b75d74132bade}




Definition at line 1477 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCIN2\_\-PORT@{PSCIN2\_\-PORT}}
\index{PSCIN2\_\-PORT@{PSCIN2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCIN2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCIN2\_\-PORT~PORTD}\label{ATmega32M1_8h_dfd1f6d17382aaa46e6e703ea243f413}




Definition at line 1476 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT0A\_\-BIT@{PSCOUT0A\_\-BIT}}
\index{PSCOUT0A\_\-BIT@{PSCOUT0A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT0A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT0A\_\-BIT~0}\label{ATmega32M1_8h_d1beac66a74d5c850c506473f2f602ff}




Definition at line 1465 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT0A\_\-PORT@{PSCOUT0A\_\-PORT}}
\index{PSCOUT0A\_\-PORT@{PSCOUT0A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT0A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT0A\_\-PORT~PORTD}\label{ATmega32M1_8h_e30c429a2ae0591e3be424c40afbfddc}




Definition at line 1464 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT0B\_\-BIT@{PSCOUT0B\_\-BIT}}
\index{PSCOUT0B\_\-BIT@{PSCOUT0B\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT0B\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT0B\_\-BIT~7}\label{ATmega32M1_8h_b7d102c465395e1bb9f31ccf219b9efd}




Definition at line 1394 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT0B\_\-PORT@{PSCOUT0B\_\-PORT}}
\index{PSCOUT0B\_\-PORT@{PSCOUT0B\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT0B\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT0B\_\-PORT~PORTB}\label{ATmega32M1_8h_08b7ba38a71638f8375038463acb8bb2}




Definition at line 1393 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT1A\_\-BIT@{PSCOUT1A\_\-BIT}}
\index{PSCOUT1A\_\-BIT@{PSCOUT1A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT1A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT1A\_\-BIT~0}\label{ATmega32M1_8h_8079fb16cf069d1f45d55f141352ff41}




Definition at line 1403 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT1A\_\-PORT@{PSCOUT1A\_\-PORT}}
\index{PSCOUT1A\_\-PORT@{PSCOUT1A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT1A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT1A\_\-PORT~PORTC}\label{ATmega32M1_8h_743673182a2ef71640253365990b053c}




Definition at line 1402 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT1B\_\-BIT@{PSCOUT1B\_\-BIT}}
\index{PSCOUT1B\_\-BIT@{PSCOUT1B\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT1B\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT1B\_\-BIT~6}\label{ATmega32M1_8h_e25fb4f676760502951640a9c3d83a2c}




Definition at line 1387 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT1B\_\-PORT@{PSCOUT1B\_\-PORT}}
\index{PSCOUT1B\_\-PORT@{PSCOUT1B\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT1B\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT1B\_\-PORT~PORTB}\label{ATmega32M1_8h_047efe256b88f9d5b01a6e7aa091e686}




Definition at line 1386 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT2A\_\-BIT@{PSCOUT2A\_\-BIT}}
\index{PSCOUT2A\_\-BIT@{PSCOUT2A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT2A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT2A\_\-BIT~0}\label{ATmega32M1_8h_18e1c2e6c2731037578334dfa9d1fc25}




Definition at line 1343 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT2A\_\-PORT@{PSCOUT2A\_\-PORT}}
\index{PSCOUT2A\_\-PORT@{PSCOUT2A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT2A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT2A\_\-PORT~PORTB}\label{ATmega32M1_8h_491770fdfba121a25e8d5a6f31b1f2b3}




Definition at line 1342 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT2B\_\-BIT@{PSCOUT2B\_\-BIT}}
\index{PSCOUT2B\_\-BIT@{PSCOUT2B\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT2B\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT2B\_\-BIT~1}\label{ATmega32M1_8h_a4749926adf87fbe1429235428519f72}




Definition at line 1350 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSCOUT2B\_\-PORT@{PSCOUT2B\_\-PORT}}
\index{PSCOUT2B\_\-PORT@{PSCOUT2B\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSCOUT2B\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define PSCOUT2B\_\-PORT~PORTB}\label{ATmega32M1_8h_f7838f3354f6bff84e8c74fc8ac476d9}




Definition at line 1349 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSR10\_\-REG@{PSR10\_\-REG}}
\index{PSR10\_\-REG@{PSR10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSR10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSR10\_\-REG~GTCCR}\label{ATmega32M1_8h_1899597272e570e57bb170dab76baa82}




Definition at line 785 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSRSYNC\_\-REG@{PSRSYNC\_\-REG}}
\index{PSRSYNC\_\-REG@{PSRSYNC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSRSYNC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSRSYNC\_\-REG~GTCCR}\label{ATmega32M1_8h_628a64a640746546004768242b9a2144}




Definition at line 788 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSYNC00\_\-REG@{PSYNC00\_\-REG}}
\index{PSYNC00\_\-REG@{PSYNC00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSYNC00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSYNC00\_\-REG~PSYNC}\label{ATmega32M1_8h_9338c7a4cf2d617c2f07d9ab83c49449}




Definition at line 777 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSYNC01\_\-REG@{PSYNC01\_\-REG}}
\index{PSYNC01\_\-REG@{PSYNC01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSYNC01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSYNC01\_\-REG~PSYNC}\label{ATmega32M1_8h_5ebd0b1df26719d9076d649a083555d4}




Definition at line 778 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSYNC10\_\-REG@{PSYNC10\_\-REG}}
\index{PSYNC10\_\-REG@{PSYNC10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSYNC10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSYNC10\_\-REG~PSYNC}\label{ATmega32M1_8h_7c6c782b7a875ce89ba8604675d3772b}




Definition at line 779 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSYNC11\_\-REG@{PSYNC11\_\-REG}}
\index{PSYNC11\_\-REG@{PSYNC11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSYNC11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSYNC11\_\-REG~PSYNC}\label{ATmega32M1_8h_9743bab09ccc3d442cc4895cc9bc0d8c}




Definition at line 780 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSYNC20\_\-REG@{PSYNC20\_\-REG}}
\index{PSYNC20\_\-REG@{PSYNC20\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSYNC20\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSYNC20\_\-REG~PSYNC}\label{ATmega32M1_8h_1212360793d8d050981471afe6fc2b1d}




Definition at line 781 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PSYNC21\_\-REG@{PSYNC21\_\-REG}}
\index{PSYNC21\_\-REG@{PSYNC21\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PSYNC21\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PSYNC21\_\-REG~PSYNC}\label{ATmega32M1_8h_b09123bda96f0cc082abb1ce52fa67e0}




Definition at line 782 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PUD\_\-REG@{PUD\_\-REG}}
\index{PUD\_\-REG@{PUD\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PUD\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PUD\_\-REG~MCUCR}\label{ATmega32M1_8h_4695ce5358406651354ca4f021d1d2d6}




Definition at line 972 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PULOCK\_\-REG@{PULOCK\_\-REG}}
\index{PULOCK\_\-REG@{PULOCK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PULOCK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define PULOCK\_\-REG~PCNF}\label{ATmega32M1_8h_d5e16cd1161196feb2aec184cbccbb12}




Definition at line 1143 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PWM0A\_\-NUM@{PWM0A\_\-NUM}}
\index{PWM0A\_\-NUM@{PWM0A\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PWM0A\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define PWM0A\_\-NUM~0}\label{ATmega32M1_8h_26a4d91e8c8b3e6bda070e62ef0d0e9c}




Definition at line 87 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PWM0B\_\-NUM@{PWM0B\_\-NUM}}
\index{PWM0B\_\-NUM@{PWM0B\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PWM0B\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define PWM0B\_\-NUM~1}\label{ATmega32M1_8h_4bbb228e78b5a8052d9366675b4ddb88}




Definition at line 88 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PWM1A\_\-NUM@{PWM1A\_\-NUM}}
\index{PWM1A\_\-NUM@{PWM1A\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PWM1A\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define PWM1A\_\-NUM~2}\label{ATmega32M1_8h_fc895f54605ed61bfbe2cda6c31b216e}




Definition at line 89 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PWM1B\_\-NUM@{PWM1B\_\-NUM}}
\index{PWM1B\_\-NUM@{PWM1B\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PWM1B\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define PWM1B\_\-NUM~3}\label{ATmega32M1_8h_d83fb739b3594fe37719f65cca2470eb}




Definition at line 90 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!PWM\_\-TOTAL\_\-NUM@{PWM\_\-TOTAL\_\-NUM}}
\index{PWM\_\-TOTAL\_\-NUM@{PWM\_\-TOTAL\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[PWM\_\-TOTAL\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define PWM\_\-TOTAL\_\-NUM~4}\label{ATmega32M1_8h_7cb4da096f48116b7ab3d837e16dd1e1}




Definition at line 91 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RB0TAG\_\-REG@{RB0TAG\_\-REG}}
\index{RB0TAG\_\-REG@{RB0TAG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RB0TAG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RB0TAG\_\-REG~CANIDT4}\label{ATmega32M1_8h_79fd9d6b48681a4411a96c61886b088f}




Definition at line 727 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RB1TAG\_\-REG@{RB1TAG\_\-REG}}
\index{RB1TAG\_\-REG@{RB1TAG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RB1TAG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RB1TAG\_\-REG~CANIDT4}\label{ATmega32M1_8h_e27ab9f89ac764f76962f18fec54efc7}




Definition at line 728 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!REFS0\_\-REG@{REFS0\_\-REG}}
\index{REFS0\_\-REG@{REFS0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[REFS0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define REFS0\_\-REG~ADMUX}\label{ATmega32M1_8h_68b29d640322aade8917f668742ff817}




Definition at line 262 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!REFS1\_\-REG@{REFS1\_\-REG}}
\index{REFS1\_\-REG@{REFS1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[REFS1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define REFS1\_\-REG~ADMUX}\label{ATmega32M1_8h_35bc81dac549141d8b63a5ecc5c67db4}




Definition at line 263 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RESET\_\-BIT@{RESET\_\-BIT}}
\index{RESET\_\-BIT@{RESET\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RESET\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define RESET\_\-BIT~0}\label{ATmega32M1_8h_66f55ddd405ba42949ed56b895cc0fb7}




Definition at line 1533 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RESET\_\-PORT@{RESET\_\-PORT}}
\index{RESET\_\-PORT@{RESET\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RESET\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define RESET\_\-PORT~PORTE}\label{ATmega32M1_8h_1ed4280c556a9f6d63204cc3ad5b3523}




Definition at line 1532 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RPLV\_\-REG@{RPLV\_\-REG}}
\index{RPLV\_\-REG@{RPLV\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RPLV\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RPLV\_\-REG~CANCDMOB}\label{ATmega32M1_8h_f98c9b4c13be2e69a9691078cc6c2125}




Definition at line 796 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RTRMSK\_\-REG@{RTRMSK\_\-REG}}
\index{RTRMSK\_\-REG@{RTRMSK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RTRMSK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RTRMSK\_\-REG~CANIDM4}\label{ATmega32M1_8h_6e59758d0e734e612bae2b60e3411533}




Definition at line 479 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RTRTAG\_\-REG@{RTRTAG\_\-REG}}
\index{RTRTAG\_\-REG@{RTRTAG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RTRTAG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RTRTAG\_\-REG~CANIDT4}\label{ATmega32M1_8h_4ff773e53180a6539503051279b3c589}




Definition at line 729 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RWWSB\_\-REG@{RWWSB\_\-REG}}
\index{RWWSB\_\-REG@{RWWSB\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RWWSB\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RWWSB\_\-REG~SPMCSR}\label{ATmega32M1_8h_a49c40927ba6e250afac9c32118398d9}




Definition at line 1136 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RWWSRE\_\-REG@{RWWSRE\_\-REG}}
\index{RWWSRE\_\-REG@{RWWSRE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RWWSRE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RWWSRE\_\-REG~SPMCSR}\label{ATmega32M1_8h_5a79ba3615229f283e1e74d46b6800a3}




Definition at line 1134 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXBSY\_\-REG@{RXBSY\_\-REG}}
\index{RXBSY\_\-REG@{RXBSY\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXBSY\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RXBSY\_\-REG~CANGSTA}\label{ATmega32M1_8h_5cc13ef6dd82014e9ef20dd53e4d56cf}




Definition at line 289 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXCAN\_\-BIT@{RXCAN\_\-BIT}}
\index{RXCAN\_\-BIT@{RXCAN\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXCAN\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define RXCAN\_\-BIT~3}\label{ATmega32M1_8h_a958d49731bc8dd21930e037ac297121}




Definition at line 1426 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXCAN\_\-PORT@{RXCAN\_\-PORT}}
\index{RXCAN\_\-PORT@{RXCAN\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXCAN\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define RXCAN\_\-PORT~PORTC}\label{ATmega32M1_8h_81c78903edae37a68920b7ba312aedc3}




Definition at line 1425 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXD\_\-BIT@{RXD\_\-BIT}}
\index{RXD\_\-BIT@{RXD\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXD\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define RXD\_\-BIT~4}\label{ATmega32M1_8h_c1439ba54cb215c5ba9d09c8da128774}




Definition at line 1501 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXD\_\-PORT@{RXD\_\-PORT}}
\index{RXD\_\-PORT@{RXD\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXD\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define RXD\_\-PORT~PORTD}\label{ATmega32M1_8h_6d8d72188e1656149662c43ae1a7d65d}




Definition at line 1500 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXLIN\_\-BIT@{RXLIN\_\-BIT}}
\index{RXLIN\_\-BIT@{RXLIN\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXLIN\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define RXLIN\_\-BIT~4}\label{ATmega32M1_8h_5256ab75e61b3eb156e62bebc0e9af37}




Definition at line 1503 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXLIN\_\-PORT@{RXLIN\_\-PORT}}
\index{RXLIN\_\-PORT@{RXLIN\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXLIN\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define RXLIN\_\-PORT~PORTD}\label{ATmega32M1_8h_d57cdc163cf7609a96834e08c3333e53}




Definition at line 1502 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!RXOK\_\-REG@{RXOK\_\-REG}}
\index{RXOK\_\-REG@{RXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[RXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define RXOK\_\-REG~CANSTMOB}\label{ATmega32M1_8h_01f1627fd0b4f9f8dba3950f75cd337b}




Definition at line 997 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!S\_\-REG@{S\_\-REG}}
\index{S\_\-REG@{S\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[S\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define S\_\-REG~SREG}\label{ATmega32M1_8h_d5c67a4893fa78c73eb10898d520766a}




Definition at line 912 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SCK\_\-A\_\-BIT@{SCK\_\-A\_\-BIT}}
\index{SCK\_\-A\_\-BIT@{SCK\_\-A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SCK\_\-A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define SCK\_\-A\_\-BIT~4}\label{ATmega32M1_8h_639ba3c9a05c5db9b55402f98cc0a026}




Definition at line 1507 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SCK\_\-A\_\-PORT@{SCK\_\-A\_\-PORT}}
\index{SCK\_\-A\_\-PORT@{SCK\_\-A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SCK\_\-A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define SCK\_\-A\_\-PORT~PORTD}\label{ATmega32M1_8h_5620743ceabefe48e2c85b052e9b795b}




Definition at line 1506 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SCK\_\-BIT@{SCK\_\-BIT}}
\index{SCK\_\-BIT@{SCK\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SCK\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define SCK\_\-BIT~7}\label{ATmega32M1_8h_6d12b7ff5235cf11e01d8771862f150e}




Definition at line 1396 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SCK\_\-PORT@{SCK\_\-PORT}}
\index{SCK\_\-PORT@{SCK\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SCK\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define SCK\_\-PORT~PORTB}\label{ATmega32M1_8h_9d8cdd2fdd0e182f61d2adbf9679ede0}




Definition at line 1395 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SE\_\-REG@{SE\_\-REG}}
\index{SE\_\-REG@{SE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SE\_\-REG~SMCR}\label{ATmega32M1_8h_3753fa832d100be472ba02984bafbb97}




Definition at line 875 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SERG\_\-REG@{SERG\_\-REG}}
\index{SERG\_\-REG@{SERG\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SERG\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SERG\_\-REG~CANGIT}\label{ATmega32M1_8h_7c4aff08e98ac30717754cc364d2db4d}




Definition at line 590 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SERR\_\-REG@{SERR\_\-REG}}
\index{SERR\_\-REG@{SERR\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SERR\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SERR\_\-REG~CANSTMOB}\label{ATmega32M1_8h_94d061721828242be04b01aef62bb060}




Definition at line 995 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-INPUT\_\-CAPTURE1\_\-NUM@{SIG\_\-INPUT\_\-CAPTURE1\_\-NUM}}
\index{SIG\_\-INPUT\_\-CAPTURE1\_\-NUM@{SIG\_\-INPUT\_\-CAPTURE1\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-INPUT\_\-CAPTURE1\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-INPUT\_\-CAPTURE1\_\-NUM~0}\label{ATmega32M1_8h_0c87454bc091184215305e24524b2daf}




Definition at line 94 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM@{SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM}}
\index{SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM@{SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-INPUT\_\-CAPTURE\_\-TOTAL\_\-NUM~1}\label{ATmega32M1_8h_c42ea58970ddffa0fa9ee4be1fed0f2e}




Definition at line 95 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM}}
\index{SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OUTPUT\_\-COMPARE0A\_\-NUM~0}\label{ATmega32M1_8h_d3b7b674796226bbd43f40729527742a}




Definition at line 80 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM}}
\index{SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OUTPUT\_\-COMPARE0B\_\-NUM~1}\label{ATmega32M1_8h_af9fdd09778af08c30379ea871073bdd}




Definition at line 81 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM}}
\index{SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OUTPUT\_\-COMPARE1A\_\-NUM~2}\label{ATmega32M1_8h_8408f4acff57cfdd5d0fa1b75efbdf82}




Definition at line 82 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM}}
\index{SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OUTPUT\_\-COMPARE1B\_\-NUM~3}\label{ATmega32M1_8h_2a83b7ecaaa93887915fb1fa10ffd988}




Definition at line 83 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM}}
\index{SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM@{SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OUTPUT\_\-COMPARE\_\-TOTAL\_\-NUM~4}\label{ATmega32M1_8h_b79e450e7a2efdb68b3284986e261eb6}




Definition at line 84 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OVERFLOW0\_\-NUM@{SIG\_\-OVERFLOW0\_\-NUM}}
\index{SIG\_\-OVERFLOW0\_\-NUM@{SIG\_\-OVERFLOW0\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OVERFLOW0\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OVERFLOW0\_\-NUM~0}\label{ATmega32M1_8h_dc2c1549d25c6f392c3142151e6b5ad9}




Definition at line 75 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OVERFLOW1\_\-NUM@{SIG\_\-OVERFLOW1\_\-NUM}}
\index{SIG\_\-OVERFLOW1\_\-NUM@{SIG\_\-OVERFLOW1\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OVERFLOW1\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OVERFLOW1\_\-NUM~1}\label{ATmega32M1_8h_f350cb76b8d5ff2b88b7c605b04ef67e}




Definition at line 76 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM@{SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM}}
\index{SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM@{SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM]{\setlength{\rightskip}{0pt plus 5cm}\#define SIG\_\-OVERFLOW\_\-TOTAL\_\-NUM~2}\label{ATmega32M1_8h_2d8b8ff307d3ab929cbfe927dcb4dedb}




Definition at line 77 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIGRD\_\-REG@{SIGRD\_\-REG}}
\index{SIGRD\_\-REG@{SIGRD\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIGRD\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIGRD\_\-REG~SPMCSR}\label{ATmega32M1_8h_073b29aae3c3f2175ad89495285d0839}




Definition at line 1135 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIT0\_\-REG@{SIT0\_\-REG}}
\index{SIT0\_\-REG@{SIT0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIT0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIT0\_\-REG~CANSIT2}\label{ATmega32M1_8h_69c3318dc4b59735d780d49586ce158b}




Definition at line 660 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIT1\_\-REG@{SIT1\_\-REG}}
\index{SIT1\_\-REG@{SIT1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIT1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIT1\_\-REG~CANSIT2}\label{ATmega32M1_8h_786f3e8e21b2a0359280ee92dc45a8ed}




Definition at line 661 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIT2\_\-REG@{SIT2\_\-REG}}
\index{SIT2\_\-REG@{SIT2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIT2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIT2\_\-REG~CANSIT2}\label{ATmega32M1_8h_e4a709f19027cfbb4c38a47377fa1ccb}




Definition at line 662 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIT3\_\-REG@{SIT3\_\-REG}}
\index{SIT3\_\-REG@{SIT3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIT3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIT3\_\-REG~CANSIT2}\label{ATmega32M1_8h_a3231a8a801751f63a44cde8c236f5c3}




Definition at line 663 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIT4\_\-REG@{SIT4\_\-REG}}
\index{SIT4\_\-REG@{SIT4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIT4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIT4\_\-REG~CANSIT2}\label{ATmega32M1_8h_2797003e9a913cc58ce20b8f82bf94c6}




Definition at line 664 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SIT5\_\-REG@{SIT5\_\-REG}}
\index{SIT5\_\-REG@{SIT5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SIT5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SIT5\_\-REG~CANSIT2}\label{ATmega32M1_8h_55a7b2775ed80a32117b98e2e07bd173}




Definition at line 665 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SJW0\_\-REG@{SJW0\_\-REG}}
\index{SJW0\_\-REG@{SJW0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SJW0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SJW0\_\-REG~CANBT2}\label{ATmega32M1_8h_e54bc95ba473d1f8b1fcebb591bec736}




Definition at line 1149 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SJW1\_\-REG@{SJW1\_\-REG}}
\index{SJW1\_\-REG@{SJW1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SJW1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SJW1\_\-REG~CANBT2}\label{ATmega32M1_8h_ac4cc0e5076a81c654f8aa0875fe3349}




Definition at line 1150 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SM0\_\-REG@{SM0\_\-REG}}
\index{SM0\_\-REG@{SM0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SM0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SM0\_\-REG~SMCR}\label{ATmega32M1_8h_ecdc6672d1da1703528bb4c6a175cccd}




Definition at line 876 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SM1\_\-REG@{SM1\_\-REG}}
\index{SM1\_\-REG@{SM1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SM1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SM1\_\-REG~SMCR}\label{ATmega32M1_8h_cf3ed9d8a05266beda14d174c478aafe}




Definition at line 877 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SM2\_\-REG@{SM2\_\-REG}}
\index{SM2\_\-REG@{SM2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SM2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SM2\_\-REG~SMCR}\label{ATmega32M1_8h_518ceb13930595fb924655cf11ca929f}




Definition at line 878 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SMP\_\-REG@{SMP\_\-REG}}
\index{SMP\_\-REG@{SMP\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SMP\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SMP\_\-REG~CANBT3}\label{ATmega32M1_8h_2c44ceadee631f27e5c9794c38ef5c97}




Definition at line 1153 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP0\_\-REG@{SP0\_\-REG}}
\index{SP0\_\-REG@{SP0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP0\_\-REG~SPL}\label{ATmega32M1_8h_5608c5fb647d16f5100e81ba32d53321}




Definition at line 841 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP10\_\-REG@{SP10\_\-REG}}
\index{SP10\_\-REG@{SP10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP10\_\-REG~SPH}\label{ATmega32M1_8h_82b9e11bea11d7278380f73ebd8b3e65}




Definition at line 803 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP11\_\-REG@{SP11\_\-REG}}
\index{SP11\_\-REG@{SP11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP11\_\-REG~SPH}\label{ATmega32M1_8h_83a324a8dfc1aefa1ecf888731fb8038}




Definition at line 804 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP12\_\-REG@{SP12\_\-REG}}
\index{SP12\_\-REG@{SP12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP12\_\-REG~SPH}\label{ATmega32M1_8h_0507d8ec64852e32084acbb2a1f02c73}




Definition at line 805 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP13\_\-REG@{SP13\_\-REG}}
\index{SP13\_\-REG@{SP13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP13\_\-REG~SPH}\label{ATmega32M1_8h_7cd2a6caf6bc98d15733f3392ce831fe}




Definition at line 806 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP14\_\-REG@{SP14\_\-REG}}
\index{SP14\_\-REG@{SP14\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP14\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP14\_\-REG~SPH}\label{ATmega32M1_8h_20f5e9c3debe0298791627de76aa4d02}




Definition at line 807 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP15\_\-REG@{SP15\_\-REG}}
\index{SP15\_\-REG@{SP15\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP15\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP15\_\-REG~SPH}\label{ATmega32M1_8h_97fdf98f15cbbfebbb2d0bb9ad8bda2d}




Definition at line 808 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP1\_\-REG@{SP1\_\-REG}}
\index{SP1\_\-REG@{SP1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP1\_\-REG~SPL}\label{ATmega32M1_8h_dcc9607ff34ab7b4442d36474ff4e64f}




Definition at line 842 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP2\_\-REG@{SP2\_\-REG}}
\index{SP2\_\-REG@{SP2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP2\_\-REG~SPL}\label{ATmega32M1_8h_1c046e06f5d6f64e29defa4a461881f6}




Definition at line 843 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP3\_\-REG@{SP3\_\-REG}}
\index{SP3\_\-REG@{SP3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP3\_\-REG~SPL}\label{ATmega32M1_8h_51ab7d3611a5aac013930eed859dc8dd}




Definition at line 844 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP4\_\-REG@{SP4\_\-REG}}
\index{SP4\_\-REG@{SP4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP4\_\-REG~SPL}\label{ATmega32M1_8h_6b1c6fa1974ceeef4a00a305a06e7196}




Definition at line 845 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP5\_\-REG@{SP5\_\-REG}}
\index{SP5\_\-REG@{SP5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP5\_\-REG~SPL}\label{ATmega32M1_8h_5fbfd4d58925f91318ad6134055bef03}




Definition at line 846 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP6\_\-REG@{SP6\_\-REG}}
\index{SP6\_\-REG@{SP6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP6\_\-REG~SPL}\label{ATmega32M1_8h_c0f324075c96f94eee13eb815e489011}




Definition at line 847 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP7\_\-REG@{SP7\_\-REG}}
\index{SP7\_\-REG@{SP7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP7\_\-REG~SPL}\label{ATmega32M1_8h_02c78d91b95bbb40b4b353bef14004b1}




Definition at line 848 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP8\_\-REG@{SP8\_\-REG}}
\index{SP8\_\-REG@{SP8\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP8\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP8\_\-REG~SPH}\label{ATmega32M1_8h_604be5836f953abd148459e518e6da83}




Definition at line 801 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SP9\_\-REG@{SP9\_\-REG}}
\index{SP9\_\-REG@{SP9\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SP9\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SP9\_\-REG~SPH}\label{ATmega32M1_8h_947920343c0f3c53df283bd7dc6415a8}




Definition at line 802 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR0\_\-REG@{SPDR0\_\-REG}}
\index{SPDR0\_\-REG@{SPDR0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR0\_\-REG~SPDR}\label{ATmega32M1_8h_e286d1a386e37005b9d33ee8781e5198}




Definition at line 737 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR1\_\-REG@{SPDR1\_\-REG}}
\index{SPDR1\_\-REG@{SPDR1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR1\_\-REG~SPDR}\label{ATmega32M1_8h_f40c61e455863cc19bac9e54791a50f8}




Definition at line 738 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR2\_\-REG@{SPDR2\_\-REG}}
\index{SPDR2\_\-REG@{SPDR2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR2\_\-REG~SPDR}\label{ATmega32M1_8h_cd9796a2ab7b1a9a89105425c9cf294b}




Definition at line 739 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR3\_\-REG@{SPDR3\_\-REG}}
\index{SPDR3\_\-REG@{SPDR3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR3\_\-REG~SPDR}\label{ATmega32M1_8h_e1c964da24dbd8109ec3c90c69e78218}




Definition at line 740 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR4\_\-REG@{SPDR4\_\-REG}}
\index{SPDR4\_\-REG@{SPDR4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR4\_\-REG~SPDR}\label{ATmega32M1_8h_ca43310cbbf5ea67c095b3dfc9437b34}




Definition at line 741 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR5\_\-REG@{SPDR5\_\-REG}}
\index{SPDR5\_\-REG@{SPDR5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR5\_\-REG~SPDR}\label{ATmega32M1_8h_b0f3b8e641df5b65f70b54cab463c7b7}




Definition at line 742 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR6\_\-REG@{SPDR6\_\-REG}}
\index{SPDR6\_\-REG@{SPDR6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR6\_\-REG~SPDR}\label{ATmega32M1_8h_92c3248d93896bbec6d887e27857ff08}




Definition at line 743 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPDR7\_\-REG@{SPDR7\_\-REG}}
\index{SPDR7\_\-REG@{SPDR7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPDR7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPDR7\_\-REG~SPDR}\label{ATmega32M1_8h_2905bb24119fdabe4a060868aad2ada4}




Definition at line 744 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPE\_\-REG@{SPE\_\-REG}}
\index{SPE\_\-REG@{SPE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPE\_\-REG~SPCR}\label{ATmega32M1_8h_497e4f232fae50934427462563aa5283}




Definition at line 717 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPI2X\_\-REG@{SPI2X\_\-REG}}
\index{SPI2X\_\-REG@{SPI2X\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPI2X\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPI2X\_\-REG~SPSR}\label{ATmega32M1_8h_a6662a9529be90e21a08fee8d528f3ba}




Definition at line 206 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPIE\_\-REG@{SPIE\_\-REG}}
\index{SPIE\_\-REG@{SPIE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPIE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPIE\_\-REG~SPCR}\label{ATmega32M1_8h_4a6335b178fe328bd1d084920d22dc00}




Definition at line 718 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPIF\_\-REG@{SPIF\_\-REG}}
\index{SPIF\_\-REG@{SPIF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPIF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPIF\_\-REG~SPSR}\label{ATmega32M1_8h_20bcff325abee56d7bde984028c2cb00}




Definition at line 208 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPIPS\_\-REG@{SPIPS\_\-REG}}
\index{SPIPS\_\-REG@{SPIPS\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPIPS\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPIPS\_\-REG~MCUCR}\label{ATmega32M1_8h_cdac9e8330ec5bd8b0fa4a9e082f5ba5}




Definition at line 973 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPMEN\_\-REG@{SPMEN\_\-REG}}
\index{SPMEN\_\-REG@{SPMEN\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPMEN\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPMEN\_\-REG~SPMCSR}\label{ATmega32M1_8h_4de612ee44ba85f90ac3cf6e3c3afed9}




Definition at line 1130 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPMIE\_\-REG@{SPMIE\_\-REG}}
\index{SPMIE\_\-REG@{SPMIE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPMIE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPMIE\_\-REG~SPMCSR}\label{ATmega32M1_8h_5da07c9aab4947a615b084b35617d357}




Definition at line 1137 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPR0\_\-REG@{SPR0\_\-REG}}
\index{SPR0\_\-REG@{SPR0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPR0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPR0\_\-REG~SPCR}\label{ATmega32M1_8h_f13a1c9cc5f642805db9db0c921a7e02}




Definition at line 711 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SPR1\_\-REG@{SPR1\_\-REG}}
\index{SPR1\_\-REG@{SPR1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SPR1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SPR1\_\-REG~SPCR}\label{ATmega32M1_8h_9a0ee0d8d33bf697c23db9b29b1d64c5}




Definition at line 712 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SS\_\-A\_\-BIT@{SS\_\-A\_\-BIT}}
\index{SS\_\-A\_\-BIT@{SS\_\-A\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SS\_\-A\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define SS\_\-A\_\-BIT~1}\label{ATmega32M1_8h_6adde53b8266ec6506be100b5c7a985f}




Definition at line 1412 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SS\_\-A\_\-PORT@{SS\_\-A\_\-PORT}}
\index{SS\_\-A\_\-PORT@{SS\_\-A\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SS\_\-A\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define SS\_\-A\_\-PORT~PORTC}\label{ATmega32M1_8h_07cac9ccc5f381f35b750b2572762cb2}




Definition at line 1411 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SS\_\-BIT@{SS\_\-BIT}}
\index{SS\_\-BIT@{SS\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SS\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define SS\_\-BIT~3}\label{ATmega32M1_8h_ae0ac70a6df5c7c06ff1dcb4eb88847e}




Definition at line 1492 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SS\_\-PORT@{SS\_\-PORT}}
\index{SS\_\-PORT@{SS\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SS\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define SS\_\-PORT~PORTD}\label{ATmega32M1_8h_8be2af1591c35ac1a02de5cfd395cdf0}




Definition at line 1491 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SWRES\_\-REG@{SWRES\_\-REG}}
\index{SWRES\_\-REG@{SWRES\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SWRES\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SWRES\_\-REG~CANGCON}\label{ATmega32M1_8h_375024eff04456f565a4c8b0f1c90f2c}




Definition at line 294 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!SYNTTC\_\-REG@{SYNTTC\_\-REG}}
\index{SYNTTC\_\-REG@{SYNTTC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[SYNTTC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define SYNTTC\_\-REG~CANGCON}\label{ATmega32M1_8h_26e04b2f0d03bb1c1029a36db48f9223}




Definition at line 298 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!T0\_\-BIT@{T0\_\-BIT}}
\index{T0\_\-BIT@{T0\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[T0\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define T0\_\-BIT~2}\label{ATmega32M1_8h_adb4f7772697cd095ae5fb90aeec659f}




Definition at line 1417 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!T0\_\-PORT@{T0\_\-PORT}}
\index{T0\_\-PORT@{T0\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[T0\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define T0\_\-PORT~PORTC}\label{ATmega32M1_8h_217613f31ebd791655795b26f7344827}




Definition at line 1416 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!T1\_\-BIT@{T1\_\-BIT}}
\index{T1\_\-BIT@{T1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[T1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define T1\_\-BIT~3}\label{ATmega32M1_8h_6b1b354771b6b266871a21b61a791f93}




Definition at line 1424 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!T1\_\-PORT@{T1\_\-PORT}}
\index{T1\_\-PORT@{T1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[T1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define T1\_\-PORT~PORTC}\label{ATmega32M1_8h_ba3d5aa9f89c5aecc954aa7a4abc38c1}




Definition at line 1423 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!T\_\-REG@{T\_\-REG}}
\index{T\_\-REG@{T\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[T\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define T\_\-REG~SREG}\label{ATmega32M1_8h_109aeb5473f651bba0263dbf92c97221}




Definition at line 914 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-0\_\-REG@{TCNT0\_\-0\_\-REG}}
\index{TCNT0\_\-0\_\-REG@{TCNT0\_\-0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-0\_\-REG~TCNT0}\label{ATmega32M1_8h_c1f8fccfbb821380dfd50315f3f538cb}




Definition at line 632 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-1\_\-REG@{TCNT0\_\-1\_\-REG}}
\index{TCNT0\_\-1\_\-REG@{TCNT0\_\-1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-1\_\-REG~TCNT0}\label{ATmega32M1_8h_fefb95d2e9de396641a5c8508afc6296}




Definition at line 633 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-2\_\-REG@{TCNT0\_\-2\_\-REG}}
\index{TCNT0\_\-2\_\-REG@{TCNT0\_\-2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-2\_\-REG~TCNT0}\label{ATmega32M1_8h_65ae573967a4ed2b4c8a214668d8819a}




Definition at line 634 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-3\_\-REG@{TCNT0\_\-3\_\-REG}}
\index{TCNT0\_\-3\_\-REG@{TCNT0\_\-3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-3\_\-REG~TCNT0}\label{ATmega32M1_8h_f63de593254505c1f2bca9431ebd488c}




Definition at line 635 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-4\_\-REG@{TCNT0\_\-4\_\-REG}}
\index{TCNT0\_\-4\_\-REG@{TCNT0\_\-4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-4\_\-REG~TCNT0}\label{ATmega32M1_8h_72502a03cb165c8e4b17719ae81bf4d3}




Definition at line 636 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-5\_\-REG@{TCNT0\_\-5\_\-REG}}
\index{TCNT0\_\-5\_\-REG@{TCNT0\_\-5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-5\_\-REG~TCNT0}\label{ATmega32M1_8h_0be8f29978a33d59b4bd325e5a085558}




Definition at line 637 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-6\_\-REG@{TCNT0\_\-6\_\-REG}}
\index{TCNT0\_\-6\_\-REG@{TCNT0\_\-6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-6\_\-REG~TCNT0}\label{ATmega32M1_8h_86097e27c8c0d84023574094a043d6de}




Definition at line 638 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT0\_\-7\_\-REG@{TCNT0\_\-7\_\-REG}}
\index{TCNT0\_\-7\_\-REG@{TCNT0\_\-7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT0\_\-7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT0\_\-7\_\-REG~TCNT0}\label{ATmega32M1_8h_9921b9c8a6f52d305a1c2334012063db}




Definition at line 639 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H0\_\-REG@{TCNT1H0\_\-REG}}
\index{TCNT1H0\_\-REG@{TCNT1H0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H0\_\-REG~TCNT1H}\label{ATmega32M1_8h_a25ece3bdccc712500a9fb51af5fe557}




Definition at line 319 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H1\_\-REG@{TCNT1H1\_\-REG}}
\index{TCNT1H1\_\-REG@{TCNT1H1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H1\_\-REG~TCNT1H}\label{ATmega32M1_8h_d97ed8249b922cc19cecc021c12ea783}




Definition at line 320 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H2\_\-REG@{TCNT1H2\_\-REG}}
\index{TCNT1H2\_\-REG@{TCNT1H2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H2\_\-REG~TCNT1H}\label{ATmega32M1_8h_f578b228d973cb4d616eb51d37765697}




Definition at line 321 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H3\_\-REG@{TCNT1H3\_\-REG}}
\index{TCNT1H3\_\-REG@{TCNT1H3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H3\_\-REG~TCNT1H}\label{ATmega32M1_8h_5627b674239b3c237b3327a6fe72bbbd}




Definition at line 322 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H4\_\-REG@{TCNT1H4\_\-REG}}
\index{TCNT1H4\_\-REG@{TCNT1H4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H4\_\-REG~TCNT1H}\label{ATmega32M1_8h_23dc0075885d6a295d9b2044f65170d0}




Definition at line 323 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H5\_\-REG@{TCNT1H5\_\-REG}}
\index{TCNT1H5\_\-REG@{TCNT1H5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H5\_\-REG~TCNT1H}\label{ATmega32M1_8h_93aa52885a457f46936c4501fdad82ff}




Definition at line 324 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H6\_\-REG@{TCNT1H6\_\-REG}}
\index{TCNT1H6\_\-REG@{TCNT1H6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H6\_\-REG~TCNT1H}\label{ATmega32M1_8h_4d94dde3b93ff056ff7ceb0774907803}




Definition at line 325 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1H7\_\-REG@{TCNT1H7\_\-REG}}
\index{TCNT1H7\_\-REG@{TCNT1H7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1H7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1H7\_\-REG~TCNT1H}\label{ATmega32M1_8h_94072c2c6d4a730d86ad0a3d91375e44}




Definition at line 326 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L0\_\-REG@{TCNT1L0\_\-REG}}
\index{TCNT1L0\_\-REG@{TCNT1L0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L0\_\-REG~TCNT1L}\label{ATmega32M1_8h_188d60f8d09fc037b9c5a8cb850f620d}




Definition at line 1093 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L1\_\-REG@{TCNT1L1\_\-REG}}
\index{TCNT1L1\_\-REG@{TCNT1L1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L1\_\-REG~TCNT1L}\label{ATmega32M1_8h_7ae20ef3144cb261ffbc188904aa6fc8}




Definition at line 1094 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L2\_\-REG@{TCNT1L2\_\-REG}}
\index{TCNT1L2\_\-REG@{TCNT1L2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L2\_\-REG~TCNT1L}\label{ATmega32M1_8h_9d359e3c9797388743e07f62cd6a7f69}




Definition at line 1095 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L3\_\-REG@{TCNT1L3\_\-REG}}
\index{TCNT1L3\_\-REG@{TCNT1L3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L3\_\-REG~TCNT1L}\label{ATmega32M1_8h_60acfda9c5f3665a29d7fc035cc14e9f}




Definition at line 1096 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L4\_\-REG@{TCNT1L4\_\-REG}}
\index{TCNT1L4\_\-REG@{TCNT1L4\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L4\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L4\_\-REG~TCNT1L}\label{ATmega32M1_8h_3372b7f2a7af05e0763489f98de9acbb}




Definition at line 1097 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L5\_\-REG@{TCNT1L5\_\-REG}}
\index{TCNT1L5\_\-REG@{TCNT1L5\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L5\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L5\_\-REG~TCNT1L}\label{ATmega32M1_8h_b799b9cca3dc49d5eeccb878498a54d6}




Definition at line 1098 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L6\_\-REG@{TCNT1L6\_\-REG}}
\index{TCNT1L6\_\-REG@{TCNT1L6\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L6\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L6\_\-REG~TCNT1L}\label{ATmega32M1_8h_0b9c322bd0d2e05fba2d599682f68577}




Definition at line 1099 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TCNT1L7\_\-REG@{TCNT1L7\_\-REG}}
\index{TCNT1L7\_\-REG@{TCNT1L7\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TCNT1L7\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TCNT1L7\_\-REG~TCNT1L}\label{ATmega32M1_8h_d79699eade7a8ffaa386919f3b7495df}




Definition at line 1100 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TEST\_\-REG@{TEST\_\-REG}}
\index{TEST\_\-REG@{TEST\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TEST\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TEST\_\-REG~CANGCON}\label{ATmega32M1_8h_61408a9ad43461009da1ac44330f457d}




Definition at line 296 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-AVAILABLE@{TIMER0\_\-AVAILABLE}}
\index{TIMER0\_\-AVAILABLE@{TIMER0\_\-AVAILABLE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-AVAILABLE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-AVAILABLE}\label{ATmega32M1_8h_668b697532f623f63297039e0cb41619}




Definition at line 67 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-0@{TIMER0\_\-PRESCALER\_\-DIV\_\-0}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-0@{TIMER0\_\-PRESCALER\_\-DIV\_\-0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-0]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-0~0}\label{ATmega32M1_8h_c66ec013fa597474117c127351bedced}




Definition at line 28 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-1@{TIMER0\_\-PRESCALER\_\-DIV\_\-1}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-1@{TIMER0\_\-PRESCALER\_\-DIV\_\-1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-1]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-1~1}\label{ATmega32M1_8h_d60a9603ee404b402b1b7652b419614a}




Definition at line 29 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-1024@{TIMER0\_\-PRESCALER\_\-DIV\_\-1024}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-1024@{TIMER0\_\-PRESCALER\_\-DIV\_\-1024}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-1024]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-1024~5}\label{ATmega32M1_8h_972da851dcc6b09922511e1284edc36e}




Definition at line 33 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-256@{TIMER0\_\-PRESCALER\_\-DIV\_\-256}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-256@{TIMER0\_\-PRESCALER\_\-DIV\_\-256}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-256]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-256~4}\label{ATmega32M1_8h_668e89427212bdd50a9fc22780627bdd}




Definition at line 32 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-64@{TIMER0\_\-PRESCALER\_\-DIV\_\-64}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-64@{TIMER0\_\-PRESCALER\_\-DIV\_\-64}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-64]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-64~3}\label{ATmega32M1_8h_1ff030cae6ddd509d1dc8a34ef020a10}




Definition at line 31 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-8@{TIMER0\_\-PRESCALER\_\-DIV\_\-8}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-8@{TIMER0\_\-PRESCALER\_\-DIV\_\-8}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-8]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-8~2}\label{ATmega32M1_8h_83262dc8806bd35b95e39c7f4ad660dc}




Definition at line 30 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-FALL@{TIMER0\_\-PRESCALER\_\-DIV\_\-FALL}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-FALL@{TIMER0\_\-PRESCALER\_\-DIV\_\-FALL}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-FALL]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-FALL~6}\label{ATmega32M1_8h_c67439191efe80613cbefa35399a776f}




Definition at line 34 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-DIV\_\-RISE@{TIMER0\_\-PRESCALER\_\-DIV\_\-RISE}}
\index{TIMER0\_\-PRESCALER\_\-DIV\_\-RISE@{TIMER0\_\-PRESCALER\_\-DIV\_\-RISE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-DIV\_\-RISE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-DIV\_\-RISE~7}\label{ATmega32M1_8h_5deaad711ed0f159d7bf19beb594c577}




Definition at line 35 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-0@{TIMER0\_\-PRESCALER\_\-REG\_\-0}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-0@{TIMER0\_\-PRESCALER\_\-REG\_\-0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-0]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-0~0}\label{ATmega32M1_8h_8143ac91326ffcd96d2acd33924cc3aa}




Definition at line 37 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-1@{TIMER0\_\-PRESCALER\_\-REG\_\-1}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-1@{TIMER0\_\-PRESCALER\_\-REG\_\-1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-1]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-1~1}\label{ATmega32M1_8h_c88125b4d75100eb292b9a366c4bd5c6}




Definition at line 38 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-2@{TIMER0\_\-PRESCALER\_\-REG\_\-2}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-2@{TIMER0\_\-PRESCALER\_\-REG\_\-2}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-2]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-2~8}\label{ATmega32M1_8h_655e86d55af2afe0033b3d8bf2aceb20}




Definition at line 39 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-3@{TIMER0\_\-PRESCALER\_\-REG\_\-3}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-3@{TIMER0\_\-PRESCALER\_\-REG\_\-3}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-3]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-3~64}\label{ATmega32M1_8h_cae86407c26e1b79197011862a53b366}




Definition at line 40 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-4@{TIMER0\_\-PRESCALER\_\-REG\_\-4}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-4@{TIMER0\_\-PRESCALER\_\-REG\_\-4}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-4]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-4~256}\label{ATmega32M1_8h_6c2a877eb19568271dd956d347d22372}




Definition at line 41 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-5@{TIMER0\_\-PRESCALER\_\-REG\_\-5}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-5@{TIMER0\_\-PRESCALER\_\-REG\_\-5}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-5]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-5~1024}\label{ATmega32M1_8h_042c7933f29f1014ba3277b5103e6186}




Definition at line 42 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-6@{TIMER0\_\-PRESCALER\_\-REG\_\-6}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-6@{TIMER0\_\-PRESCALER\_\-REG\_\-6}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-6]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-6~-1}\label{ATmega32M1_8h_95d957994107d6a2b5c7f6fa9453322d}




Definition at line 43 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0\_\-PRESCALER\_\-REG\_\-7@{TIMER0\_\-PRESCALER\_\-REG\_\-7}}
\index{TIMER0\_\-PRESCALER\_\-REG\_\-7@{TIMER0\_\-PRESCALER\_\-REG\_\-7}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0\_\-PRESCALER\_\-REG\_\-7]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0\_\-PRESCALER\_\-REG\_\-7~-2}\label{ATmega32M1_8h_0b5413f6b78514d3aa97adbc8be48895}




Definition at line 44 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0A\_\-AVAILABLE@{TIMER0A\_\-AVAILABLE}}
\index{TIMER0A\_\-AVAILABLE@{TIMER0A\_\-AVAILABLE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0A\_\-AVAILABLE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0A\_\-AVAILABLE}\label{ATmega32M1_8h_3cc243a0fd45f898830730fbfc85db5b}




Definition at line 68 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER0B\_\-AVAILABLE@{TIMER0B\_\-AVAILABLE}}
\index{TIMER0B\_\-AVAILABLE@{TIMER0B\_\-AVAILABLE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER0B\_\-AVAILABLE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER0B\_\-AVAILABLE}\label{ATmega32M1_8h_3a9fca32601aee812eddafca2bb5ba17}




Definition at line 69 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-AVAILABLE@{TIMER1\_\-AVAILABLE}}
\index{TIMER1\_\-AVAILABLE@{TIMER1\_\-AVAILABLE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-AVAILABLE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-AVAILABLE}\label{ATmega32M1_8h_6d3318366877ea390df999396fa2231f}




Definition at line 70 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-0@{TIMER1\_\-PRESCALER\_\-DIV\_\-0}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-0@{TIMER1\_\-PRESCALER\_\-DIV\_\-0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-0]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-0~0}\label{ATmega32M1_8h_f1c1d4d979d1f563be962db8b145fbbf}




Definition at line 47 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-1@{TIMER1\_\-PRESCALER\_\-DIV\_\-1}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-1@{TIMER1\_\-PRESCALER\_\-DIV\_\-1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-1]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-1~1}\label{ATmega32M1_8h_00903327b93ba9aa8e5b61d970854436}




Definition at line 48 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-1024@{TIMER1\_\-PRESCALER\_\-DIV\_\-1024}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-1024@{TIMER1\_\-PRESCALER\_\-DIV\_\-1024}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-1024]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-1024~5}\label{ATmega32M1_8h_0ad10baa71b1ca91c19048016f05017c}




Definition at line 52 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-256@{TIMER1\_\-PRESCALER\_\-DIV\_\-256}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-256@{TIMER1\_\-PRESCALER\_\-DIV\_\-256}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-256]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-256~4}\label{ATmega32M1_8h_39b2b2e4d200fcfc3d3e37c639509709}




Definition at line 51 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-64@{TIMER1\_\-PRESCALER\_\-DIV\_\-64}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-64@{TIMER1\_\-PRESCALER\_\-DIV\_\-64}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-64]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-64~3}\label{ATmega32M1_8h_d45561073141104680888376d87c045c}




Definition at line 50 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-8@{TIMER1\_\-PRESCALER\_\-DIV\_\-8}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-8@{TIMER1\_\-PRESCALER\_\-DIV\_\-8}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-8]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-8~2}\label{ATmega32M1_8h_8d2fa60e55354b71578efeebc62c2041}




Definition at line 49 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-FALL@{TIMER1\_\-PRESCALER\_\-DIV\_\-FALL}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-FALL@{TIMER1\_\-PRESCALER\_\-DIV\_\-FALL}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-FALL]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-FALL~6}\label{ATmega32M1_8h_7b199b12c9d8ba4918086bcade103877}




Definition at line 53 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-DIV\_\-RISE@{TIMER1\_\-PRESCALER\_\-DIV\_\-RISE}}
\index{TIMER1\_\-PRESCALER\_\-DIV\_\-RISE@{TIMER1\_\-PRESCALER\_\-DIV\_\-RISE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-DIV\_\-RISE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-DIV\_\-RISE~7}\label{ATmega32M1_8h_c93d79b825cdef098fda6da0cb4ac583}




Definition at line 54 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-0@{TIMER1\_\-PRESCALER\_\-REG\_\-0}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-0@{TIMER1\_\-PRESCALER\_\-REG\_\-0}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-0]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-0~0}\label{ATmega32M1_8h_c09431aad889913350bf739bd1e551f8}




Definition at line 56 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-1@{TIMER1\_\-PRESCALER\_\-REG\_\-1}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-1@{TIMER1\_\-PRESCALER\_\-REG\_\-1}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-1]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-1~1}\label{ATmega32M1_8h_3ca66f6a9cf2c7dd589bf1f839b8ca53}




Definition at line 57 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-2@{TIMER1\_\-PRESCALER\_\-REG\_\-2}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-2@{TIMER1\_\-PRESCALER\_\-REG\_\-2}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-2]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-2~8}\label{ATmega32M1_8h_609a70f0a21cc0402185cb2bc3987c98}




Definition at line 58 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-3@{TIMER1\_\-PRESCALER\_\-REG\_\-3}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-3@{TIMER1\_\-PRESCALER\_\-REG\_\-3}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-3]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-3~64}\label{ATmega32M1_8h_dc43c349d2e4c5bac8815c65cb54c547}




Definition at line 59 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-4@{TIMER1\_\-PRESCALER\_\-REG\_\-4}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-4@{TIMER1\_\-PRESCALER\_\-REG\_\-4}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-4]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-4~256}\label{ATmega32M1_8h_b5bf5eadef1837eec749d1fc167e30a0}




Definition at line 60 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-5@{TIMER1\_\-PRESCALER\_\-REG\_\-5}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-5@{TIMER1\_\-PRESCALER\_\-REG\_\-5}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-5]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-5~1024}\label{ATmega32M1_8h_7b96ecfe303fdcc1c5bf136fe7a961ed}




Definition at line 61 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-6@{TIMER1\_\-PRESCALER\_\-REG\_\-6}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-6@{TIMER1\_\-PRESCALER\_\-REG\_\-6}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-6]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-6~-1}\label{ATmega32M1_8h_d600912867da52934f54803c6fbf8c6c}




Definition at line 62 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1\_\-PRESCALER\_\-REG\_\-7@{TIMER1\_\-PRESCALER\_\-REG\_\-7}}
\index{TIMER1\_\-PRESCALER\_\-REG\_\-7@{TIMER1\_\-PRESCALER\_\-REG\_\-7}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1\_\-PRESCALER\_\-REG\_\-7]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1\_\-PRESCALER\_\-REG\_\-7~-2}\label{ATmega32M1_8h_b9b860fdea605509ceca7a558534f127}




Definition at line 63 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1A\_\-AVAILABLE@{TIMER1A\_\-AVAILABLE}}
\index{TIMER1A\_\-AVAILABLE@{TIMER1A\_\-AVAILABLE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1A\_\-AVAILABLE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1A\_\-AVAILABLE}\label{ATmega32M1_8h_6526dc8015a1b35402fb96c638a26d53}




Definition at line 71 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TIMER1B\_\-AVAILABLE@{TIMER1B\_\-AVAILABLE}}
\index{TIMER1B\_\-AVAILABLE@{TIMER1B\_\-AVAILABLE}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TIMER1B\_\-AVAILABLE]{\setlength{\rightskip}{0pt plus 5cm}\#define TIMER1B\_\-AVAILABLE}\label{ATmega32M1_8h_6a0280541886cc87863f94b8c9fc11d3}




Definition at line 72 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TOIE0\_\-REG@{TOIE0\_\-REG}}
\index{TOIE0\_\-REG@{TOIE0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TOIE0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TOIE0\_\-REG~TIMSK0}\label{ATmega32M1_8h_5a635571a56f1fb59e3b884aa073d512}




Definition at line 1200 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TOIE1\_\-REG@{TOIE1\_\-REG}}
\index{TOIE1\_\-REG@{TOIE1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TOIE1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TOIE1\_\-REG~TIMSK1}\label{ATmega32M1_8h_72a162fa56af8033ce7ef5691d9c0800}




Definition at line 1205 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TOV0\_\-REG@{TOV0\_\-REG}}
\index{TOV0\_\-REG@{TOV0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TOV0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TOV0\_\-REG~TIFR0}\label{ATmega32M1_8h_09d5f62889c143cea3fa808f861dfb42}




Definition at line 1329 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TOV1\_\-REG@{TOV1\_\-REG}}
\index{TOV1\_\-REG@{TOV1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TOV1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TOV1\_\-REG~TIFR1}\label{ATmega32M1_8h_790eacbd141db2ee7206f580472434d0}




Definition at line 721 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TSM\_\-REG@{TSM\_\-REG}}
\index{TSM\_\-REG@{TSM\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TSM\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TSM\_\-REG~GTCCR}\label{ATmega32M1_8h_632ccca1330e774c17d0222764857134}




Definition at line 787 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TTC\_\-REG@{TTC\_\-REG}}
\index{TTC\_\-REG@{TTC\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TTC\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TTC\_\-REG~CANGCON}\label{ATmega32M1_8h_2ec129d6ffd7c8f9d739573591f0d8b6}




Definition at line 299 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXBSY\_\-REG@{TXBSY\_\-REG}}
\index{TXBSY\_\-REG@{TXBSY\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXBSY\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TXBSY\_\-REG~CANGSTA}\label{ATmega32M1_8h_da3aa80ccc300ea78f0852f31d68c53e}




Definition at line 290 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXCAN\_\-BIT@{TXCAN\_\-BIT}}
\index{TXCAN\_\-BIT@{TXCAN\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXCAN\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define TXCAN\_\-BIT~2}\label{ATmega32M1_8h_45eabe333d27f57950ca102bc0b0c10c}




Definition at line 1419 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXCAN\_\-PORT@{TXCAN\_\-PORT}}
\index{TXCAN\_\-PORT@{TXCAN\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXCAN\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define TXCAN\_\-PORT~PORTC}\label{ATmega32M1_8h_d989f3c47cbcf871cc59b83b11f3f5dd}




Definition at line 1418 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXD\_\-BIT@{TXD\_\-BIT}}
\index{TXD\_\-BIT@{TXD\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXD\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define TXD\_\-BIT~3}\label{ATmega32M1_8h_c46720398dddfb3e046f23b2bcaa32cb}




Definition at line 1486 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXD\_\-PORT@{TXD\_\-PORT}}
\index{TXD\_\-PORT@{TXD\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXD\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define TXD\_\-PORT~PORTD}\label{ATmega32M1_8h_2d2613c1ad00b518aa1ea26f587b890f}




Definition at line 1485 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXLIN\_\-BIT@{TXLIN\_\-BIT}}
\index{TXLIN\_\-BIT@{TXLIN\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXLIN\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define TXLIN\_\-BIT~3}\label{ATmega32M1_8h_8a9aa7c1bf02a528d48d60f56f8116c5}




Definition at line 1488 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXLIN\_\-PORT@{TXLIN\_\-PORT}}
\index{TXLIN\_\-PORT@{TXLIN\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXLIN\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define TXLIN\_\-PORT~PORTD}\label{ATmega32M1_8h_39a6e1a6cde47fad116863a9b7a6ff2d}




Definition at line 1487 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!TXOK\_\-REG@{TXOK\_\-REG}}
\index{TXOK\_\-REG@{TXOK\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[TXOK\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define TXOK\_\-REG~CANSTMOB}\label{ATmega32M1_8h_2fb1a9a8ecafe572b5763cfc780bfe4a}




Definition at line 998 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!V\_\-REG@{V\_\-REG}}
\index{V\_\-REG@{V\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[V\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define V\_\-REG~SREG}\label{ATmega32M1_8h_dc5c29a5cd7ad49dd65b3d5543d81264}




Definition at line 911 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WCOL\_\-REG@{WCOL\_\-REG}}
\index{WCOL\_\-REG@{WCOL\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WCOL\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WCOL\_\-REG~SPSR}\label{ATmega32M1_8h_8690f4e7baac3f8ebb35ab606e72926f}




Definition at line 207 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDCE\_\-REG@{WDCE\_\-REG}}
\index{WDCE\_\-REG@{WDCE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDCE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDCE\_\-REG~WDTCSR}\label{ATmega32M1_8h_09b8a372add8b4e03dd2d48af366873c}




Definition at line 148 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDE\_\-REG@{WDE\_\-REG}}
\index{WDE\_\-REG@{WDE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDE\_\-REG~WDTCSR}\label{ATmega32M1_8h_68a534a0c5a59a929e184874ac9ea541}




Definition at line 147 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDIE\_\-REG@{WDIE\_\-REG}}
\index{WDIE\_\-REG@{WDIE\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDIE\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDIE\_\-REG~WDTCSR}\label{ATmega32M1_8h_5bb401bda2071e4416f81c2fa26a3d7d}




Definition at line 150 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDIF\_\-REG@{WDIF\_\-REG}}
\index{WDIF\_\-REG@{WDIF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDIF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDIF\_\-REG~WDTCSR}\label{ATmega32M1_8h_ce95db9638b9dd95b4332e5a9eee338b}




Definition at line 151 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDP0\_\-REG@{WDP0\_\-REG}}
\index{WDP0\_\-REG@{WDP0\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDP0\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDP0\_\-REG~WDTCSR}\label{ATmega32M1_8h_fccf8ccff2dddf330d1f5f8875fad1f6}




Definition at line 144 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDP1\_\-REG@{WDP1\_\-REG}}
\index{WDP1\_\-REG@{WDP1\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDP1\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDP1\_\-REG~WDTCSR}\label{ATmega32M1_8h_79c1ffde21945ce60b0afaf033c9980a}




Definition at line 145 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDP2\_\-REG@{WDP2\_\-REG}}
\index{WDP2\_\-REG@{WDP2\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDP2\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDP2\_\-REG~WDTCSR}\label{ATmega32M1_8h_b8152b6da120a011179dc54061670ac5}




Definition at line 146 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDP3\_\-REG@{WDP3\_\-REG}}
\index{WDP3\_\-REG@{WDP3\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDP3\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDP3\_\-REG~WDTCSR}\label{ATmega32M1_8h_fd294c509a61d6df051e540ab7be192e}




Definition at line 149 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WDRF\_\-REG@{WDRF\_\-REG}}
\index{WDRF\_\-REG@{WDRF\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WDRF\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WDRF\_\-REG~MCUSR}\label{ATmega32M1_8h_8733752726a2bd869e92714e64e0714b}




Definition at line 854 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM00\_\-REG@{WGM00\_\-REG}}
\index{WGM00\_\-REG@{WGM00\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM00\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM00\_\-REG~TCCR0A}\label{ATmega32M1_8h_7d46975ec4154199bf50380121ce600e}




Definition at line 682 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM01\_\-REG@{WGM01\_\-REG}}
\index{WGM01\_\-REG@{WGM01\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM01\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM01\_\-REG~TCCR0A}\label{ATmega32M1_8h_67cab651d9a52a906ef4c4394b7599bf}




Definition at line 683 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM02\_\-REG@{WGM02\_\-REG}}
\index{WGM02\_\-REG@{WGM02\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM02\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM02\_\-REG~TCCR0B}\label{ATmega32M1_8h_14aec6e45f5112cedf2524c61386e08f}




Definition at line 671 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM10\_\-REG@{WGM10\_\-REG}}
\index{WGM10\_\-REG@{WGM10\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM10\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM10\_\-REG~TCCR1A}\label{ATmega32M1_8h_8386f95ea03a1d528d6cbf6ed6d276fa}




Definition at line 1055 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM11\_\-REG@{WGM11\_\-REG}}
\index{WGM11\_\-REG@{WGM11\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM11\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM11\_\-REG~TCCR1A}\label{ATmega32M1_8h_f6f01fc86adb28e5bc25c6cec893bf51}




Definition at line 1056 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM12\_\-REG@{WGM12\_\-REG}}
\index{WGM12\_\-REG@{WGM12\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM12\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM12\_\-REG~TCCR1B}\label{ATmega32M1_8h_b2e99bfd4f6ec85c547b6c907ac95d46}




Definition at line 1116 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!WGM13\_\-REG@{WGM13\_\-REG}}
\index{WGM13\_\-REG@{WGM13\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[WGM13\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define WGM13\_\-REG~TCCR1B}\label{ATmega32M1_8h_2cc5c4157481bce6d6dd7108d0db5946}




Definition at line 1117 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!XTAL1\_\-BIT@{XTAL1\_\-BIT}}
\index{XTAL1\_\-BIT@{XTAL1\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[XTAL1\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define XTAL1\_\-BIT~1}\label{ATmega32M1_8h_c419f26dad9c1cc0438778e94e9ff32e}




Definition at line 1542 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!XTAL1\_\-PORT@{XTAL1\_\-PORT}}
\index{XTAL1\_\-PORT@{XTAL1\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[XTAL1\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define XTAL1\_\-PORT~PORTE}\label{ATmega32M1_8h_402e3c82644975582e7abc97cae556ab}




Definition at line 1541 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!XTAL2\_\-BIT@{XTAL2\_\-BIT}}
\index{XTAL2\_\-BIT@{XTAL2\_\-BIT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[XTAL2\_\-BIT]{\setlength{\rightskip}{0pt plus 5cm}\#define XTAL2\_\-BIT~2}\label{ATmega32M1_8h_d597998e468122779bbc707f4d4c8514}




Definition at line 1549 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!XTAL2\_\-PORT@{XTAL2\_\-PORT}}
\index{XTAL2\_\-PORT@{XTAL2\_\-PORT}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[XTAL2\_\-PORT]{\setlength{\rightskip}{0pt plus 5cm}\#define XTAL2\_\-PORT~PORTE}\label{ATmega32M1_8h_012abcc74571b8e1c02784f13c1d4883}




Definition at line 1548 of file ATmega32M1.h.\index{ATmega32M1.h@{ATmega32M1.h}!Z\_\-REG@{Z\_\-REG}}
\index{Z\_\-REG@{Z\_\-REG}!ATmega32M1.h@{ATmega32M1.h}}
\subsubsection[Z\_\-REG]{\setlength{\rightskip}{0pt plus 5cm}\#define Z\_\-REG~SREG}\label{ATmega32M1_8h_c14906b36c9bea67d3374e5015a1d0a2}




Definition at line 909 of file ATmega32M1.h.