\section{aversive\_\-10-03-12/modules/comm/i2c/i2c.h File Reference}
\label{i2c_8h}\index{aversive\_\-10-03-12/modules/comm/i2c/i2c.h@{aversive\_\-10-03-12/modules/comm/i2c/i2c.h}}
{\tt \#include $<$aversive.h$>$}\par
{\tt \#include $<$i2c\_\-config.h$>$}\par
\subsection*{Defines}
\begin{CompactItemize}
\item 
\#define {\bf I2C\_\-DEBUG}~1
\item 
\#define {\bf I2C\_\-ADD\_\-GENCALL}~0x00
\item 
\#define {\bf I2C\_\-ADD\_\-MASTER}~0x80
\item 
\#define {\bf I2C\_\-CTRL\_\-GENERIC}~0x00
\item 
\#define {\bf I2C\_\-CTRL\_\-SYNC}~0x01
\item 
\#define {\bf I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS}~0x02
\item 
\#define {\bf I2C\_\-STATUS\_\-READY}~0x00
\item 
\#define {\bf I2C\_\-STATUS\_\-MASTER\_\-XMIT}~0x01
\item 
\#define {\bf I2C\_\-STATUS\_\-MASTER\_\-RECV}~0x02
\item 
\#define {\bf I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT}~0x04
\item 
\#define {\bf I2C\_\-STATUS\_\-SLAVE\_\-XMIT}~0x08
\item 
\#define {\bf I2C\_\-STATUS\_\-SLAVE\_\-RECV}~0x10
\item 
\#define {\bf I2C\_\-STATUS\_\-OP\_\-FINISHED}~0x20
\item 
\#define {\bf I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT}~0x40
\item 
\#define {\bf I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT}~0x80
\end{CompactItemize}
\subsection*{Enumerations}
\begin{CompactItemize}
\item 
enum {\bf i2c\_\-mode\_\-t} \{ {\bf I2C\_\-MODE\_\-UNINIT}, 
{\bf I2C\_\-MODE\_\-SLAVE}
 \}
\end{CompactItemize}
\subsection*{Functions}
\begin{CompactItemize}
\item 
void {\bf i2c\_\-init} ({\bf i2c\_\-mode\_\-t} mode, uint8\_\-t add)
\item 
void {\bf i2c\_\-register\_\-recv\_\-event} (void($\ast${\bf event})(uint8\_\-t $\ast$, int8\_\-t))
\item 
void {\bf i2c\_\-register\_\-recv\_\-byte\_\-event} (void($\ast${\bf event})(uint8\_\-t, uint8\_\-t, uint8\_\-t))
\item 
void {\bf i2c\_\-register\_\-send\_\-event} (void($\ast${\bf event})(int8\_\-t))
\item 
int8\_\-t {\bf i2c\_\-send} (uint8\_\-t dest\_\-add, uint8\_\-t $\ast$buf, uint8\_\-t size, uint8\_\-t ctrl)
\item 
int8\_\-t {\bf i2c\_\-resend} (void)
\item 
int8\_\-t {\bf i2c\_\-rerecv} (void)
\item 
void {\bf i2c\_\-release\_\-bus} (void)
\item 
int8\_\-t {\bf i2c\_\-recv} (uint8\_\-t dest\_\-add, uint8\_\-t size, uint8\_\-t ctrl)
\item 
int8\_\-t {\bf i2c\_\-flush} (void)
\item 
uint8\_\-t {\bf i2c\_\-set\_\-recv\_\-size} (uint8\_\-t size)
\item 
{\bf i2c\_\-mode\_\-t} {\bf i2c\_\-mode} (void)
\item 
uint8\_\-t {\bf i2c\_\-status} (void)
\item 
uint8\_\-t {\bf i2c\_\-get\_\-recv\_\-buffer} (uint8\_\-t $\ast$buf, uint8\_\-t size)
\item 
void {\bf i2c\_\-reset} (void)
\item 
void {\bf i2c\_\-debug} (void)
\end{CompactItemize}


\subsection{Define Documentation}
\index{i2c.h@{i2c.h}!I2C\_\-ADD\_\-GENCALL@{I2C\_\-ADD\_\-GENCALL}}
\index{I2C\_\-ADD\_\-GENCALL@{I2C\_\-ADD\_\-GENCALL}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-ADD\_\-GENCALL]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-ADD\_\-GENCALL~0x00}\label{i2c_8h_778c136909deea5fc859c4619d83f7de}




Definition at line 55 of file i2c.h.\index{i2c.h@{i2c.h}!I2C\_\-ADD\_\-MASTER@{I2C\_\-ADD\_\-MASTER}}
\index{I2C\_\-ADD\_\-MASTER@{I2C\_\-ADD\_\-MASTER}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-ADD\_\-MASTER]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-ADD\_\-MASTER~0x80}\label{i2c_8h_b1c26315ac2fbbf0e10df79675a69461}




Definition at line 59 of file i2c.h.

Referenced by i2c\_\-recv(), and i2c\_\-send().\index{i2c.h@{i2c.h}!I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS@{I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS}}
\index{I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS@{I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS~0x02}\label{i2c_8h_729c2f5179c20bd7aeabe248f588b71a}


when the operation is finished as a master, don't release the bus (don't send any stop condition). You can send several commands without beeing interrupted by another master. To release it, send another command without this flag or just call \doxyref{i2c\_\-release\_\-bus()}{p.}{i2c_8c_5222b4067cf31018763371bbd2021115}. This has no effect on a slave. 

Definition at line 89 of file i2c.h.

Referenced by SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-CTRL\_\-GENERIC@{I2C\_\-CTRL\_\-GENERIC}}
\index{I2C\_\-CTRL\_\-GENERIC@{I2C\_\-CTRL\_\-GENERIC}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-CTRL\_\-GENERIC]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-CTRL\_\-GENERIC~0x00}\label{i2c_8h_fbc07e0a517f58fdff21ebbe0d8e487c}




Definition at line 76 of file i2c.h.\index{i2c.h@{i2c.h}!I2C\_\-CTRL\_\-SYNC@{I2C\_\-CTRL\_\-SYNC}}
\index{I2C\_\-CTRL\_\-SYNC@{I2C\_\-CTRL\_\-SYNC}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-CTRL\_\-SYNC]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-CTRL\_\-SYNC~0x01}\label{i2c_8h_55ee56dac483af7fd71d45e318405b8b}


Error code is returned instead of beeing sent as a callback. Note that the send\_\-event callback is \_\-not\_\- called if it is registered. This functions waits and only returns when the transmission is finished or if it failed. Note that there is no timeout, so it can loop forever... WARNING : irq MUST be allowed 

Definition at line 83 of file i2c.h.

Referenced by i2c\_\-recv(), i2c\_\-send(), and SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-DEBUG@{I2C\_\-DEBUG}}
\index{I2C\_\-DEBUG@{I2C\_\-DEBUG}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-DEBUG]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-DEBUG~1}\label{i2c_8h_7a2aac31b5f76ba87c190d25c050a00f}


please read carefully !

this implementation of the i2c interface is very specific this is a multi bus implementation. The multi bus operation is done by implementing software i2c modules (slave only)

HARDWARE I2C : --------------

This module implements i2c using the hardware twi interface of AVR devices. It can operates in slave and/or master mode, depending on the initialisation parameter. This module is interrupt driven only.

In master mode, buffer can be transmitted/received on demand (with start and stop conditions). In slave mode, operations are done asynchronously. Like some other modules in aversive, callback functions can be registered and are called on transmission or reception events.

This module should support multimaster mode, send() or \doxyref{recv()}{p.}{mf2__server_8c_9260b44a72bbdd7ba7870b7b0f352db4} depends on the address parameter. 

Definition at line 53 of file i2c.h.\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-MASTER\_\-RECV@{I2C\_\-STATUS\_\-MASTER\_\-RECV}}
\index{I2C\_\-STATUS\_\-MASTER\_\-RECV@{I2C\_\-STATUS\_\-MASTER\_\-RECV}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-MASTER\_\-RECV]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-MASTER\_\-RECV~0x02}\label{i2c_8h_e7b3bb8a5135ae96b2e3140742b96c09}




Definition at line 95 of file i2c.h.

Referenced by i2c\_\-get\_\-recv\_\-buffer(), i2c\_\-recv(), i2c\_\-send(), i2c\_\-set\_\-recv\_\-size(), and SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-MASTER\_\-XMIT@{I2C\_\-STATUS\_\-MASTER\_\-XMIT}}
\index{I2C\_\-STATUS\_\-MASTER\_\-XMIT@{I2C\_\-STATUS\_\-MASTER\_\-XMIT}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-MASTER\_\-XMIT]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-MASTER\_\-XMIT~0x01}\label{i2c_8h_cd65b0bea08b2f3772b85db74386758c}




Definition at line 94 of file i2c.h.

Referenced by i2c\_\-recv(), i2c\_\-send(), and SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT@{I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT}}
\index{I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT@{I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-NEED\_\-RECV\_\-EVT~0x80}\label{i2c_8h_ef9224e4f3e3b98c2baf06db16a5730b}




Definition at line 101 of file i2c.h.

Referenced by SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT@{I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT}}
\index{I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT@{I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-NEED\_\-XMIT\_\-EVT~0x40}\label{i2c_8h_91ac45fe9fef00635d4ed4853130f079}




Definition at line 100 of file i2c.h.

Referenced by SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-OP\_\-FINISHED@{I2C\_\-STATUS\_\-OP\_\-FINISHED}}
\index{I2C\_\-STATUS\_\-OP\_\-FINISHED@{I2C\_\-STATUS\_\-OP\_\-FINISHED}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-OP\_\-FINISHED]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-OP\_\-FINISHED~0x20}\label{i2c_8h_830e1b2909d0375ec9847765bd938f24}




Definition at line 99 of file i2c.h.

Referenced by i2c\_\-recv(), i2c\_\-send(), and SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-READY@{I2C\_\-STATUS\_\-READY}}
\index{I2C\_\-STATUS\_\-READY@{I2C\_\-STATUS\_\-READY}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-READY]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-READY~0x00}\label{i2c_8h_21e1c7edb8d7bfc26b1d9ba3be611ac9}




Definition at line 93 of file i2c.h.

Referenced by i2c\_\-init(), i2c\_\-recv(), and i2c\_\-reset().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-SLAVE\_\-RECV@{I2C\_\-STATUS\_\-SLAVE\_\-RECV}}
\index{I2C\_\-STATUS\_\-SLAVE\_\-RECV@{I2C\_\-STATUS\_\-SLAVE\_\-RECV}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-SLAVE\_\-RECV]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-SLAVE\_\-RECV~0x10}\label{i2c_8h_53df9369c965982c8aecbe3f08f77fba}




Definition at line 98 of file i2c.h.

Referenced by i2c\_\-get\_\-recv\_\-buffer(), i2c\_\-recv(), i2c\_\-send(), and SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-SLAVE\_\-XMIT@{I2C\_\-STATUS\_\-SLAVE\_\-XMIT}}
\index{I2C\_\-STATUS\_\-SLAVE\_\-XMIT@{I2C\_\-STATUS\_\-SLAVE\_\-XMIT}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-SLAVE\_\-XMIT]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-SLAVE\_\-XMIT~0x08}\label{i2c_8h_067ede496167871993867ea27d6aadda}




Definition at line 97 of file i2c.h.

Referenced by i2c\_\-recv(), i2c\_\-send(), and SIGNAL().\index{i2c.h@{i2c.h}!I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT@{I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT}}
\index{I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT@{I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT}!i2c.h@{i2c.h}}
\subsubsection[I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT]{\setlength{\rightskip}{0pt plus 5cm}\#define I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT~0x04}\label{i2c_8h_b70b40dcbd508733f6b78961d813c413}




Definition at line 96 of file i2c.h.

Referenced by i2c\_\-flush(), i2c\_\-send(), and SIGNAL().

\subsection{Enumeration Type Documentation}
\index{i2c.h@{i2c.h}!i2c\_\-mode\_\-t@{i2c\_\-mode\_\-t}}
\index{i2c\_\-mode\_\-t@{i2c\_\-mode\_\-t}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-mode\_\-t]{\setlength{\rightskip}{0pt plus 5cm}enum {\bf i2c\_\-mode\_\-t}}\label{i2c_8h_c1e2996ebee909590af8e3cc1c316c25}


\begin{Desc}
\item[Enumerator: ]\par
\begin{description}
\index{I2C\_\-MODE\_\-UNINIT@{I2C\_\-MODE\_\-UNINIT}!i2c.h@{i2c.h}}\index{i2c.h@{i2c.h}!I2C\_\-MODE\_\-UNINIT@{I2C\_\-MODE\_\-UNINIT}}\item[{\em 
I2C\_\-MODE\_\-UNINIT\label{i2c_8h_c1e2996ebee909590af8e3cc1c316c255ef040c9ce2ee61a3d08f8f7fafbc700}
}]not initialized \index{I2C\_\-MODE\_\-SLAVE@{I2C\_\-MODE\_\-SLAVE}!i2c.h@{i2c.h}}\index{i2c.h@{i2c.h}!I2C\_\-MODE\_\-SLAVE@{I2C\_\-MODE\_\-SLAVE}}\item[{\em 
I2C\_\-MODE\_\-SLAVE\label{i2c_8h_c1e2996ebee909590af8e3cc1c316c2510a3fafafb52ab45984aa5d5a17171a0}
}]Slave \end{description}
\end{Desc}



Definition at line 65 of file i2c.h.

\subsection{Function Documentation}
\index{i2c.h@{i2c.h}!i2c\_\-debug@{i2c\_\-debug}}
\index{i2c\_\-debug@{i2c\_\-debug}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-debug]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-debug (void)}\label{i2c_8h_428a9d362abde0aef578bf523f23c4ea}


display debug infos \index{i2c.h@{i2c.h}!i2c\_\-flush@{i2c\_\-flush}}
\index{i2c\_\-flush@{i2c\_\-flush}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-flush]{\setlength{\rightskip}{0pt plus 5cm}int8\_\-t i2c\_\-flush (void)}\label{i2c_8h_b70b41e07d082581ea209e319fb32d40}


Try to flush the current operation, before it is started. The i2c module is then tagged as ready. If it returns 0, the flush was a success, and \doxyref{i2c\_\-send()}{p.}{i2c_8c_560d3f33dacd2199dd9bac3a5a7afe57} can be called. Else, it means that a transmission was running. 

Definition at line 420 of file i2c.c.

References EBUSY, ESUCCESS, I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT, IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-get\_\-recv\_\-buffer@{i2c\_\-get\_\-recv\_\-buffer}}
\index{i2c\_\-get\_\-recv\_\-buffer@{i2c\_\-get\_\-recv\_\-buffer}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-get\_\-recv\_\-buffer]{\setlength{\rightskip}{0pt plus 5cm}uint8\_\-t i2c\_\-get\_\-recv\_\-buffer (uint8\_\-t $\ast$ {\em buf}, \/  uint8\_\-t {\em size})}\label{i2c_8h_e7824af2548e0a0e4d15a5420a515813}


Copy the received buffer in the buffer given as parameter. Return number of copied bytes or $<$ 0 on \doxyref{error}{p.}{structerror}. 

Definition at line 495 of file i2c.c.

References EBUSY, I2C\_\-STATUS\_\-MASTER\_\-RECV, I2C\_\-STATUS\_\-SLAVE\_\-RECV, IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-init@{i2c\_\-init}}
\index{i2c\_\-init@{i2c\_\-init}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-init]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-init ({\bf i2c\_\-mode\_\-t} {\em mode}, \/  uint8\_\-t {\em add})}\label{i2c_8h_06d2ef9760a322ed36bc2485ae2141e4}


mode is I2C\_\-MODE\_\-UNINIT, I2C\_\-MODE\_\-MASTER, I2C\_\-MODE\_\-MULTIMASTER or I2C\_\-MODE\_\-SLAVE. Parameter add is the address in slave mode, it is composed from: b7 : true if the uC can be addressed with GENCALL b0-6: slave address 

Definition at line 89 of file i2c.c.

References I2C\_\-MODE\_\-UNINIT, I2C\_\-STATUS\_\-READY, IRQ\_\-LOCK, IRQ\_\-UNLOCK, and sbi.\index{i2c.h@{i2c.h}!i2c\_\-mode@{i2c\_\-mode}}
\index{i2c\_\-mode@{i2c\_\-mode}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-mode]{\setlength{\rightskip}{0pt plus 5cm}{\bf i2c\_\-mode\_\-t} i2c\_\-mode (void)}\label{i2c_8h_1eacf5805ac520bfc7dad3d8ad12c57c}


return the current mode of the i2c module. 

Definition at line 478 of file i2c.c.\index{i2c.h@{i2c.h}!i2c\_\-recv@{i2c\_\-recv}}
\index{i2c\_\-recv@{i2c\_\-recv}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-recv]{\setlength{\rightskip}{0pt plus 5cm}int8\_\-t i2c\_\-recv (uint8\_\-t {\em dest\_\-add}, \/  uint8\_\-t {\em size}, \/  uint8\_\-t {\em ctrl})}\label{i2c_8h_1c03f80593e8304b612425659d324841}


In slave mode, it returns \doxyref{error}{p.}{structerror} and is useless (all data is received trough the callback). In master mode, if dest\_\-add is between 0 and 127, it will start to read the addressed slave. The size of the buffer to read must be specified. Return 0 on success. The 'ctrl' parameter is composed by the flags I2C\_\-CTRL\_\-SYNC and I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS

In slave mode, it returns \doxyref{error}{p.}{structerror} and is useless (all data is received trough the callback). In master mode, if dest\_\-add is between 0 and 127, it will start to read the addressed slave. The size of the buffer to read must be specified. Return 0 on success. 

Definition at line 352 of file i2c.c.

References EBUSY, EINVAL, ENXIO, ESUCCESS, I2C\_\-ADD\_\-MASTER, I2C\_\-CTRL\_\-SYNC, I2C\_\-MODE\_\-SLAVE, I2C\_\-MODE\_\-UNINIT, I2C\_\-STATUS\_\-MASTER\_\-RECV, I2C\_\-STATUS\_\-MASTER\_\-XMIT, I2C\_\-STATUS\_\-OP\_\-FINISHED, I2C\_\-STATUS\_\-READY, I2C\_\-STATUS\_\-SLAVE\_\-RECV, I2C\_\-STATUS\_\-SLAVE\_\-XMIT, IRQ\_\-LOCK, and IRQ\_\-UNLOCK.

Referenced by i2c\_\-rerecv().\index{i2c.h@{i2c.h}!i2c\_\-register\_\-recv\_\-byte\_\-event@{i2c\_\-register\_\-recv\_\-byte\_\-event}}
\index{i2c\_\-register\_\-recv\_\-byte\_\-event@{i2c\_\-register\_\-recv\_\-byte\_\-event}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-register\_\-recv\_\-byte\_\-event]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-register\_\-recv\_\-byte\_\-event (void($\ast$)(uint8\_\-t, uint8\_\-t, uint8\_\-t) {\em event})}\label{i2c_8h_880a5ff73b3bbb7da40fd1f0aca3c658}


Register a function that is called when a byte is received. Arguments of the callback are: (hwstatus, numbyte, byte). The user app can modify the g\_\-size value, which is the number of bytes to be received in the frame: this can be done by calling \doxyref{i2c\_\-set\_\-recv\_\-size()}{p.}{i2c_8c_ce99548d1f29c7e06a3ed769673e0e9b}.

Register a function that is called when a byte is received. Arguments of the callback are: (hwstatus, numbyte, byte). The user app can modify the g\_\-recv\_\-size value, which is the number of bytes to be received in the frame: this can be done by calling \doxyref{i2c\_\-set\_\-recv\_\-size()}{p.}{i2c_8c_ce99548d1f29c7e06a3ed769673e0e9b}. 

Definition at line 169 of file i2c.c.

References IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-register\_\-recv\_\-event@{i2c\_\-register\_\-recv\_\-event}}
\index{i2c\_\-register\_\-recv\_\-event@{i2c\_\-register\_\-recv\_\-event}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-register\_\-recv\_\-event]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-register\_\-recv\_\-event (void($\ast$)(uint8\_\-t $\ast$, int8\_\-t) {\em event})}\label{i2c_8h_545b66d49e0bf82c8930367ff9abf1a2}


Register a function that is called when a buffer is received. The user application is always notified when data frame is received. Arguments of the callback are:\begin{itemize}
\item (recv\_\-buf, n$>$0) if transmission succedded. The first parameter contains the address of the reception buffer and the second contains the number of received bytes.\item (NULL, err$<$0) if the transmission failed (slave not answering or arbiteration lost). The first parameter is NULL and the second contains the \doxyref{error}{p.}{structerror} code. \end{itemize}


Definition at line 153 of file i2c.c.

References IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-register\_\-send\_\-event@{i2c\_\-register\_\-send\_\-event}}
\index{i2c\_\-register\_\-send\_\-event@{i2c\_\-register\_\-send\_\-event}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-register\_\-send\_\-event]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-register\_\-send\_\-event (void($\ast$)(int8\_\-t) {\em event})}\label{i2c_8h_10a9741651e7020a6899c66bc08ec4be}


register a function that is called when a buffer is sent (or an \doxyref{error}{p.}{structerror} occured while sending) on the i2c bus. The event function is always called by software if the \doxyref{i2c\_\-send()}{p.}{i2c_8c_560d3f33dacd2199dd9bac3a5a7afe57} function returned 0. The parameter of the event function is the \doxyref{error}{p.}{structerror} code:\begin{itemize}
\item 0 if the number of transmitted bytes is equal to the size of the original send buffer, without NACK.\item $<$0 if 0 byte has been transmitted (slave not answering or arbiteration lost)\item Else, the number of transmitted bytes is given, including the one that was not acked.\end{itemize}


register a function that is called when a buffer is sent (or an \doxyref{error}{p.}{structerror} occured while sending) on the i2c bus. The event function is always called by software if the \doxyref{i2c\_\-send()}{p.}{i2c_8c_560d3f33dacd2199dd9bac3a5a7afe57} function returned 0. The parameter of the event function is the \doxyref{error}{p.}{structerror} code:\begin{itemize}
\item $<$0 if 0 byte has been transmitted (arbiteration lost)\item Else, the number of transmitted bytes is given, including the one that was not acked. \end{itemize}


Definition at line 187 of file i2c.c.

References IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-release\_\-bus@{i2c\_\-release\_\-bus}}
\index{i2c\_\-release\_\-bus@{i2c\_\-release\_\-bus}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-release\_\-bus]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-release\_\-bus (void)}\label{i2c_8h_5222b4067cf31018763371bbd2021115}


release the bus 

Definition at line 320 of file i2c.c.\index{i2c.h@{i2c.h}!i2c\_\-rerecv@{i2c\_\-rerecv}}
\index{i2c\_\-rerecv@{i2c\_\-rerecv}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-rerecv]{\setlength{\rightskip}{0pt plus 5cm}int8\_\-t i2c\_\-rerecv (void)}\label{i2c_8h_753fca9ef38792bb6296496b4a3d56cf}


same but for recv 

Definition at line 311 of file i2c.c.

References i2c\_\-recv().\index{i2c.h@{i2c.h}!i2c\_\-resend@{i2c\_\-resend}}
\index{i2c\_\-resend@{i2c\_\-resend}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-resend]{\setlength{\rightskip}{0pt plus 5cm}int8\_\-t i2c\_\-resend (void)}\label{i2c_8h_7db23666169c7abe9c0335a50667532f}


Resend the same buffer. This call is equivalent to \doxyref{i2c\_\-send()}{p.}{i2c_8c_560d3f33dacd2199dd9bac3a5a7afe57} with the same parameters as the last call. It safe to call it from the send\_\-event, but else the send buffer may have been overwritten. 

Definition at line 302 of file i2c.c.

References i2c\_\-send().\index{i2c.h@{i2c.h}!i2c\_\-reset@{i2c\_\-reset}}
\index{i2c\_\-reset@{i2c\_\-reset}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-reset]{\setlength{\rightskip}{0pt plus 5cm}void i2c\_\-reset (void)}\label{i2c_8h_f85c47697c983de6b37a6d5d44a3001d}


recover from \doxyref{error}{p.}{structerror} states

recover from \doxyref{error}{p.}{structerror} state 

Definition at line 329 of file i2c.c.

References I2C\_\-STATUS\_\-READY, IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-send@{i2c\_\-send}}
\index{i2c\_\-send@{i2c\_\-send}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-send]{\setlength{\rightskip}{0pt plus 5cm}int8\_\-t i2c\_\-send (uint8\_\-t {\em dest\_\-add}, \/  uint8\_\-t $\ast$ {\em buf}, \/  uint8\_\-t {\em size}, \/  uint8\_\-t {\em ctrl})}\label{i2c_8h_560d3f33dacd2199dd9bac3a5a7afe57}


Send a buffer. Return 0 if xmit starts correctly. On \doxyref{error}{p.}{structerror}, return $<$ 0.\begin{itemize}
\item If mode is slave, dest\_\-add should be I2C\_\-ADD\_\-MASTER, and transmission starts when the master transmits a clk.\item If mode is master and if dest\_\-add != I2C\_\-ADD\_\-MASTER, it will transmit a START condition if bus is available (the uc will act as a master)\item If mode is master and if dest\_\-add == I2C\_\-ADD\_\-MASTER, the uC will act as a slave, and data will be sent when the uC will be addressed. The transmission will be processed with these params until a \doxyref{i2c\_\-flush()}{p.}{i2c_8c_b70b41e07d082581ea209e319fb32d40} is called. The 'ctrl' parameter is composed by the flags I2C\_\-CTRL\_\-SYNC and I2C\_\-CTRL\_\-DONT\_\-RELEASE\_\-BUS \end{itemize}


Definition at line 212 of file i2c.c.

References EBUSY, EINVAL, ENXIO, ESUCCESS, I2C\_\-ADD\_\-MASTER, I2C\_\-CTRL\_\-SYNC, I2C\_\-MODE\_\-SLAVE, I2C\_\-MODE\_\-UNINIT, I2C\_\-STATUS\_\-MASTER\_\-RECV, I2C\_\-STATUS\_\-MASTER\_\-XMIT, I2C\_\-STATUS\_\-OP\_\-FINISHED, I2C\_\-STATUS\_\-SLAVE\_\-RECV, I2C\_\-STATUS\_\-SLAVE\_\-XMIT, I2C\_\-STATUS\_\-SLAVE\_\-XMIT\_\-WAIT, IRQ\_\-LOCK, and IRQ\_\-UNLOCK.

Referenced by i2c\_\-resend().\index{i2c.h@{i2c.h}!i2c\_\-set\_\-recv\_\-size@{i2c\_\-set\_\-recv\_\-size}}
\index{i2c\_\-set\_\-recv\_\-size@{i2c\_\-set\_\-recv\_\-size}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-set\_\-recv\_\-size]{\setlength{\rightskip}{0pt plus 5cm}uint8\_\-t i2c\_\-set\_\-recv\_\-size (uint8\_\-t {\em size})}\label{i2c_8h_ce99548d1f29c7e06a3ed769673e0e9b}


In MASTER RECEIVER mode, it is possible that the user application does not know the size of the buffer. You can adjust this size during transmission (generally the size can be specified at the beginning of received data, so the user app can be notified thanks to recv\_\-byte\_\-event(). Note that \doxyref{i2c\_\-set\_\-recv\_\-size()}{p.}{i2c_8c_ce99548d1f29c7e06a3ed769673e0e9b} function has to be used with careful, making sure you understand i2c protocol and this code. Return 0 on success. Note than in SLAVE RECEIVER mode, you don't have to use this function, because the master can end the transmission by sending a stop condition on the bus. 

Definition at line 447 of file i2c.c.

References EBUSY, EINVAL, ESUCCESS, I2C\_\-STATUS\_\-MASTER\_\-RECV, IRQ\_\-LOCK, and IRQ\_\-UNLOCK.\index{i2c.h@{i2c.h}!i2c\_\-status@{i2c\_\-status}}
\index{i2c\_\-status@{i2c\_\-status}!i2c.h@{i2c.h}}
\subsubsection[i2c\_\-status]{\setlength{\rightskip}{0pt plus 5cm}uint8\_\-t i2c\_\-status (void)}\label{i2c_8h_d7adbd3b7a1d80828814ab11d574b988}


return the status of the i2c module. 

Definition at line 486 of file i2c.c.